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[fpgaboy.git] / insn_ldh_ac.v
1 `ifdef EXECUTE
2         `INSN_LDH_AC: begin
3                 case (cycle)
4                 0:      begin
5                                 address <= {8'hFF,registers[`REG_C]};
6                                 if (opcode[4]) begin    // LD A,(C)
7                                         rd <= 1;
8                                 end else begin
9                                         wr <= 1;
10                                         wdata <= registers[`REG_A];
11                                 end
12                         end
13                 1:      begin
14                                 `EXEC_NEWCYCLE;
15                                 `EXEC_INC_PC;
16                         end
17                 endcase
18         end
19 `endif
20
21 `ifdef WRITEBACK
22         `INSN_LDH_AC: begin
23                 case (cycle)
24                 0:      begin /* Type F */ end
25                 1:      if (opcode[4])
26                                 registers[`REG_A] <= rdata;
27                 endcase
28         end
29 `endif
30
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