1 ////////////////////////////////////////////////////////////////////////////////
2 // Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
3 ////////////////////////////////////////////////////////////////////////////////
6 // /___/ \ / Vendor: Xilinx
7 // \ \ \/ Version : 10.1
8 // \ \ Application : xaw2verilog
9 // / / Filename : CPUDCM.v
10 // /___/ /\ Timestamp : 03/31/2008 23:51:44
14 //Command: xaw2verilog -intstyle /home/joshua/projects/fpga/FPGABoy/CPUDCM.xaw -st CPUDCM.v
16 //Device: xc3s500e-5fg320
19 // Generated by Xilinx Architecture Wizard
20 // Written for synthesis tool: XST
21 // Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
22 // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 4.90 ns
25 module CPUDCM(CLKIN_IN,
32 output CLKIN_IBUFG_OUT;
40 assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
41 BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
43 DCM_SP DCM_SP_INST (.CLKFB(GND_BIT),
62 defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
63 defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
64 defparam DCM_SP_INST.CLKFX_DIVIDE = 25;
65 defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
66 defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
67 defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
68 defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
69 defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
70 defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
71 defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
72 defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
73 defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
74 defparam DCM_SP_INST.PHASE_SHIFT = 0;
75 defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";