14 `define FLAG_Z 8'b10000000
15 `define FLAG_N 8'b01000000
16 `define FLAG_H 8'b00100000
17 `define FLAG_C 8'b00010000
19 `define STATE_FETCH 2'h0
20 `define STATE_DECODE 2'h1
21 `define STATE_EXECUTE 2'h2
22 `define STATE_WRITEBACK 2'h3
24 `define INSN_LD_reg_imm8 8'b00xxx110
25 `define INSN_HALT 8'b01110110
26 `define INSN_LD_HL_reg 8'b01110xxx
27 `define INSN_LD_reg_HL 8'b01xxx110
28 `define INSN_LD_reg_reg 8'b01xxxxxx
29 `define INSN_LD_reg_imm16 8'b00xx0001
30 `define INSN_LD_SP_HL 8'b11111001
31 `define INSN_PUSH_reg 8'b11xx0101
32 `define INSN_POP_reg 8'b11xx0001
33 `define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
34 `define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A
35 `define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy
37 `define INSN_reg_A 3'b111
38 `define INSN_reg_B 3'b000
39 `define INSN_reg_C 3'b001
40 `define INSN_reg_D 3'b010
41 `define INSN_reg_E 3'b011
42 `define INSN_reg_H 3'b100
43 `define INSN_reg_L 3'b101
44 `define INSN_reg_dHL 3'b110
45 `define INSN_reg16_BC 2'b00
46 `define INSN_reg16_DE 2'b01
47 `define INSN_reg16_HL 2'b10
48 `define INSN_reg16_SP 2'b11
49 `define INSN_stack_AF 2'b11
50 `define INSN_stack_BC 2'b00
51 `define INSN_stack_DE 2'b01
52 `define INSN_stack_HL 2'b10
53 `define INSN_alu_ADD 3'b000
54 `define INSN_alu_ADC 3'b001
55 `define INSN_alu_SUB 3'b010
56 `define INSN_alu_SBC 3'b011
57 `define INSN_alu_AND 3'b100
58 `define INSN_alu_XOR 3'b101
59 `define INSN_alu_OR 3'b110
60 `define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
64 output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
66 output reg buswr, output reg busrd);
68 reg [1:0] state = 0; /* State within this bus cycle (see STATE_*). */
69 reg [2:0] cycle = 0; /* Cycle for instructions. */
71 reg [7:0] registers[11:0];
73 reg [15:0] address; /* Address for the next bus operation. */
75 reg [7:0] opcode; /* Opcode from the current machine cycle. */
77 reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
78 reg rd = 1, wr = 0, newcycle = 1;
80 reg [7:0] tmp; /* Generic temporary reg. */
83 assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
100 always @(posedge clk)
106 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
108 busaddress <= address;
111 state <= `STATE_DECODE;
120 if (rd) rdata <= busdata;
125 address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
126 wdata <= 8'bxxxxxxxx;
127 state <= `STATE_EXECUTE;
129 `STATE_EXECUTE: begin
130 `define EXEC_INC_PC \
131 {registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
132 `define EXEC_NEXTADDR_PCINC \
133 address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
134 `define EXEC_NEWCYCLE \
135 newcycle <= 1; rd <= 1; wr <= 0
137 `INSN_LD_reg_imm8: begin
141 `EXEC_NEXTADDR_PCINC;
146 if (opcode[5:3] == `INSN_reg_dHL) begin
147 address <= {registers[`REG_H], registers[`REG_L]};
162 /* XXX Interrupts needed for HALT. */
164 `INSN_LD_HL_reg: begin
168 `INSN_reg_A: begin wdata <= registers[`REG_A]; end
169 `INSN_reg_B: begin wdata <= registers[`REG_B]; end
170 `INSN_reg_C: begin wdata <= registers[`REG_C]; end
171 `INSN_reg_D: begin wdata <= registers[`REG_D]; end
172 `INSN_reg_E: begin wdata <= registers[`REG_E]; end
173 `INSN_reg_H: begin wdata <= registers[`REG_H]; end
174 `INSN_reg_L: begin wdata <= registers[`REG_L]; end
176 address <= {registers[`REG_H], registers[`REG_L]};
185 `INSN_LD_reg_HL: begin
188 address <= {registers[`REG_H], registers[`REG_L]};
198 `INSN_LD_reg_reg: begin
202 `INSN_reg_A: begin tmp <= registers[`REG_A]; end
203 `INSN_reg_B: begin tmp <= registers[`REG_B]; end
204 `INSN_reg_C: begin tmp <= registers[`REG_C]; end
205 `INSN_reg_D: begin tmp <= registers[`REG_D]; end
206 `INSN_reg_E: begin tmp <= registers[`REG_E]; end
207 `INSN_reg_H: begin tmp <= registers[`REG_H]; end
208 `INSN_reg_L: begin tmp <= registers[`REG_L]; end
211 `INSN_LD_reg_imm16: begin
215 `EXEC_NEXTADDR_PCINC;
219 `EXEC_NEXTADDR_PCINC;
222 2: begin `EXEC_NEWCYCLE; end
225 `INSN_LD_SP_HL: begin
228 tmp <= registers[`REG_H];
233 tmp <= registers[`REG_L];
237 `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
241 address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
243 `INSN_stack_AF: wdata <= registers[`REG_A];
244 `INSN_stack_BC: wdata <= registers[`REG_B];
245 `INSN_stack_DE: wdata <= registers[`REG_D];
246 `INSN_stack_HL: wdata <= registers[`REG_H];
251 address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
253 `INSN_stack_AF: wdata <= registers[`REG_F];
254 `INSN_stack_BC: wdata <= registers[`REG_C];
255 `INSN_stack_DE: wdata <= registers[`REG_E];
256 `INSN_stack_HL: wdata <= registers[`REG_L];
259 2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end
266 `INSN_POP_reg: begin /* POP is 12 cycles! */
270 address <= {registers[`REG_SPH],registers[`REG_SPL]};
274 address <= {registers[`REG_SPH],registers[`REG_SPL]};
285 address <= {8'hFF,registers[`REG_C]};
286 if (opcode[4]) begin // LD A,(C)
290 wdata <= registers[`REG_A];
302 address <= {registers[`REG_H],registers[`REG_L]};
303 if (opcode[3]) begin // LDx A, (HL)
307 wdata <= registers[`REG_A];
317 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
318 // fffffffff fuck your shit, read from (HL) :(
320 address <= {registers[`REG_H], registers[`REG_L]};
325 `INSN_reg_A: begin tmp <= registers[`REG_A]; end
326 `INSN_reg_B: begin tmp <= registers[`REG_B]; end
327 `INSN_reg_C: begin tmp <= registers[`REG_C]; end
328 `INSN_reg_D: begin tmp <= registers[`REG_D]; end
329 `INSN_reg_E: begin tmp <= registers[`REG_E]; end
330 `INSN_reg_H: begin tmp <= registers[`REG_H]; end
331 `INSN_reg_L: begin tmp <= registers[`REG_L]; end
332 `INSN_reg_dHL: begin tmp <= rdata; end
339 state <= `STATE_WRITEBACK;
341 `STATE_WRITEBACK: begin
346 1: case (opcode[5:3])
347 `INSN_reg_A: begin registers[`REG_A] <= rdata; cycle <= 0; end
348 `INSN_reg_B: begin registers[`REG_B] <= rdata; cycle <= 0; end
349 `INSN_reg_C: begin registers[`REG_C] <= rdata; cycle <= 0; end
350 `INSN_reg_D: begin registers[`REG_D] <= rdata; cycle <= 0; end
351 `INSN_reg_E: begin registers[`REG_E] <= rdata; cycle <= 0; end
352 `INSN_reg_H: begin registers[`REG_H] <= rdata; cycle <= 0; end
353 `INSN_reg_L: begin registers[`REG_L] <= rdata; cycle <= 0; end
354 `INSN_reg_dHL: cycle <= 2;
359 /* Nothing needs happen here. */
360 /* XXX Interrupts needed for HALT. */
362 `INSN_LD_HL_reg: begin
368 `INSN_LD_reg_HL: begin
373 `INSN_reg_A: begin registers[`REG_A] <= tmp; end
374 `INSN_reg_B: begin registers[`REG_B] <= tmp; end
375 `INSN_reg_C: begin registers[`REG_C] <= tmp; end
376 `INSN_reg_D: begin registers[`REG_D] <= tmp; end
377 `INSN_reg_E: begin registers[`REG_E] <= tmp; end
378 `INSN_reg_H: begin registers[`REG_H] <= tmp; end
379 `INSN_reg_L: begin registers[`REG_L] <= tmp; end
385 `INSN_LD_reg_reg: begin
387 `INSN_reg_A: begin registers[`REG_A] <= tmp; end
388 `INSN_reg_B: begin registers[`REG_B] <= tmp; end
389 `INSN_reg_C: begin registers[`REG_C] <= tmp; end
390 `INSN_reg_D: begin registers[`REG_D] <= tmp; end
391 `INSN_reg_E: begin registers[`REG_E] <= tmp; end
392 `INSN_reg_H: begin registers[`REG_H] <= tmp; end
393 `INSN_reg_L: begin registers[`REG_L] <= tmp; end
396 `INSN_LD_reg_imm16: begin
401 `INSN_reg16_BC: registers[`REG_C] <= rdata;
402 `INSN_reg16_DE: registers[`REG_E] <= rdata;
403 `INSN_reg16_HL: registers[`REG_L] <= rdata;
404 `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
410 `INSN_reg16_BC: registers[`REG_B] <= rdata;
411 `INSN_reg16_DE: registers[`REG_D] <= rdata;
412 `INSN_reg16_HL: registers[`REG_H] <= rdata;
413 `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
419 `INSN_LD_SP_HL: begin
423 registers[`REG_SPH] <= tmp;
427 registers[`REG_SPL] <= tmp;
431 `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
434 {registers[`REG_SPH],registers[`REG_SPL]} <=
435 {registers[`REG_SPH],registers[`REG_SPL]} - 1;
439 {registers[`REG_SPH],registers[`REG_SPL]} <=
440 {registers[`REG_SPH],registers[`REG_SPL]} - 1;
447 `INSN_POP_reg: begin /* POP is 12 cycles! */
451 {registers[`REG_SPH],registers[`REG_SPL]} <=
452 {registers[`REG_SPH],registers[`REG_SPL]} + 1;
456 `INSN_stack_AF: registers[`REG_F] <= rdata;
457 `INSN_stack_BC: registers[`REG_C] <= rdata;
458 `INSN_stack_DE: registers[`REG_E] <= rdata;
459 `INSN_stack_HL: registers[`REG_L] <= rdata;
461 {registers[`REG_SPH],registers[`REG_SPL]} <=
462 {registers[`REG_SPH],registers[`REG_SPL]} + 1;
467 `INSN_stack_AF: registers[`REG_A] <= rdata;
468 `INSN_stack_BC: registers[`REG_B] <= rdata;
469 `INSN_stack_DE: registers[`REG_D] <= rdata;
470 `INSN_stack_HL: registers[`REG_H] <= rdata;
482 registers[`REG_A] <= rdata;
492 registers[`REG_A] <= rdata;
493 {registers[`REG_H],registers[`REG_L]} <=
494 opcode[4] ? // if set, LDD, else LDI
495 ({registers[`REG_H],registers[`REG_L]} - 1) :
496 ({registers[`REG_H],registers[`REG_L]} + 1);
501 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
502 /* Sit on our asses. */
504 end else begin /* Actually do the computation! */
508 registers[`REG_A] + tmp;
510 { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
512 /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
513 /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
514 registers[`REG_F][3:0]
523 state <= `STATE_FETCH;
534 reg [7:0] rom [2047:0];
536 initial $readmemh("rom.hex", rom);
537 always #10 clk <= ~clk;
544 assign data = rd ? rom[addr] : 8'bzzzzzzzz;