10 `define XOFS ((640-160)/2)
11 `define YOFS ((480-144)/2)
16 input [2:0] lcdr, lcdg, input [1:0] lcdb,
19 output reg vgavs, vgahs,
20 output wire [2:0] vgar, vgag, output wire [1:0] vgab);
22 reg [2:0] fb [23039:0];
24 reg [7:0] lcdx = 8'h00;
25 reg [7:0] lcdy = 8'h00;
26 reg [15:0] lcdfb = 16'h0000;
28 always @(posedge lcdclk)
30 /* We use BLOCKING assigns here. */
35 end else if (lcdhs) begin
38 end else if (lcdx < 160) begin
44 reg [11:0] vgax = 0, vgay = 0;
45 reg [15:0] vgafb = 16'h0000;
47 reg [2:0] failandloss;
48 assign {vgar, vgag, vgab} =
49 ((vgax > `XOFS) && (vgax < (`XOFS + 161)) && (vgay > `YOFS) && (vgay < (`YOFS + 144))) ? {failandloss[2],2'b0,failandloss[1],2'b0,failandloss[0],1'b0} :
50 ((vgax < 640) && (vgay < 480)) ? 8'b00000000 :
53 always @(posedge vgaclk)
55 if (vgax >= (`XRES + `XFPORCH + `XSYNC + `XBPORCH))
57 if (vgay >= (`YRES + `YFPORCH + `YSYNC + `YBPORCH)) begin
68 vgahs <= (vgax >= (`XRES + `XFPORCH)) && (vgax < (`XRES + `XFPORCH + `XSYNC));
69 vgavs <= (vgay >= (`YRES + `YFPORCH)) && (vgay < (`YRES + `YFPORCH + `YSYNC));
71 if ((vgax > `XOFS) && (vgax < (`XOFS + 161)) && (vgay > `YOFS) && (vgay < (`YOFS + 144))) begin
73 failandloss <= fb[vgafb + 1];
76 // Need thsi here; vgaclk >>> lcdclk
77 if ((lcdy < 144) && (lcdx < 160))
78 fb[lcdfb] <= {lcdr[2], lcdg[2], lcdb[1]};