9 reg [7:0] rom [1023:0];
10 initial $readmemh("rom.hex", rom);
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[10:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
18 module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */
24 reg [7:0] ram [127:0];
26 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
28 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
32 if (decode) // This has to go this way. The only way XST knows how to do
33 begin // block ram is chip select, write enable, and always
34 if (wr) // reading. "else if rd" does not cut it ...
35 ram[address[6:0]] <= data;
36 odata <= ram[address[6:0]];
47 // synthesis attribute ram_style of ram is block
48 reg [7:0] ram [8191:0];
50 wire decode = address[15:13] == 3'b110;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
56 if (decode) // This has to go this way. The only way XST knows how to do
57 begin // block ram is chip select, write enable, and always
58 if (wr) // reading. "else if rd" does not cut it ...
59 ram[address[12:0]] <= data;
60 odata <= ram[address[12:0]];
71 output reg [7:0] ledout = 0);
73 wire decode = address == 16'hFF51;
75 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
81 else if (decode && wr)
90 output wire [7:0] leds,
92 output wire [3:0] digits,
93 output wire [7:0] seven,
95 output wire [2:0] r, g,
97 output wire soundl, soundr);
99 wire xtalb, clk, vgaclk;
100 IBUFG iclkbuf(.O(xtalb), .I(xtal));
101 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
102 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
108 wire irq, tmrirq, lcdcirq, vblankirq;
129 wire lcdhs, lcdvs, lcdclk;
130 wire [2:0] lcdr, lcdg;
140 .vblankirq(vblankirq),
169 (state == 2'b00) ? 4'b0010 :
170 (state == 2'b01) ? 4'b0001 :
171 (state == 2'b10) ? 4'b1000 :
184 UART nouart ( /* no u */
239 .snd_data_r(soundr));
254 always #62 clk <= ~clk;