Start changing things to happen on posedge clock.

[fpgaboy.git] / LCDC.v

`define ADDR_LCDC	16'hFF40
`define ADDR_STAT	16'hFF41
`define ADDR_SCY	16'hFF42
`define ADDR_SCX	16'hFF43
`define ADDR_LY		16'hFF44
`define ADDR_LYC	16'hFF45
`define ADDR_DMA	16'hFF46
`define ADDR_BGP	16'hFF47
`define ADDR_OBP0	16'hFF48
`define ADDR_OBP1	16'hFF49
`define ADDR_WY		16'hFF4A
`define ADDR_WX		16'hFF4B

module LCDC(
	input [15:0] addr,
	inout [7:0] data,
	input clk,	// 8MHz clock
	input wr, rd,
	output wire lcdcirq,
	output wire vblankirq,
	output wire lcdclk, lcdvs, lcdhs,
	output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
	
	/***** Needed prototypes *****/
	wire [1:0] pixdata;
	
	/***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
	reg clk4 = 0;
	always @(posedge clk)
		clk4 = ~clk4;
	
	/***** LCD control registers *****/
	reg [7:0] rLCDC = 8'h00;
	reg [7:0] rSTAT = 8'h00;
	reg [7:0] rSCY = 8'b00;
	reg [7:0] rSCX = 8'b00;
	reg [7:0] rLYC = 8'b00;
	reg [7:0] rDMA = 8'b00;
	reg [7:0] rBGP = 8'b00;
	reg [7:0] rOBP0 = 8'b00;
	reg [7:0] rOBP1 = 8'b00;
	reg [7:0] rWY = 8'b00;
	reg [7:0] rWX = 8'b00;
	
	/***** Sync generation *****/
	
	/* A complete cycle takes 456 clocks.
	 * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
	 *
	 * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
	 *        1 -> in vblank and OAM/VRAM available
	 *        2 -> OAM in use - present 86 clks
	 *        3 -> OAM/VRAM in use - present 163 clks
	 * So, X = 0~162 is HActive,
	 * X = 163-369 is HBlank,
	 * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
	 * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
	 * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
	 * [02:15:40] <Judge_> some kind of delay
	 * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
	 */
	reg [8:0] posx = 9'h000;
	reg [7:0] posy = 8'h00;
	
	wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
	wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
	
	wire display = (posx > 2) && (posx < 163) && (posy < 144);
	
	wire [1:0] mode = (posy < 144) ?
				(vraminuse ? 2'b11 :
				 oaminuse ? 2'b10 :
				 2'b00)
				: 2'b01;
	
	wire [7:0] vxpos = rSCX + posx - 3;
	wire [7:0] vypos = rSCY + posy;
	
	assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
	assign lcdhs = (posx == 2) && rLCDC[7];
	assign lcdclk = clk4;
	
	wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
	wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
	wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;
	
	reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
	assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
	assign vblankirq = (posx == 0 && posy == 153);
	
	always @(posedge clk4)
	begin
		if (posx == 455) begin
			posx <= 0;
			if (posy == 153) begin
				posy <= 0;
				if (0 == rLYC)
					lycirq <= 1;
			end else begin
				posy <= posy + 1;
				/* Check for vblank and generate an IRQ if needed. */
				if (posy == 143) begin 
					mode01irq <= 1;
				end
				if ((posy + 1) == rLYC)
					lycirq <= 1;
				
			end
		end else begin
			posx <= posx + 1;
			if (posx == 165)
				mode00irq <= 1;
			else if (posx == 373)
				mode10irq <= 1;
			else begin
				mode00irq <= 0;
				mode01irq <= 0;
				mode10irq <= 0;
			end
			lycirq <= 0;
		end
		
		lcdr <= lcdr_;
		lcdg <= lcdg_;
		lcdb <= lcdb_;
	end
	
	/***** Video RAM *****/
	/* Base is 0x8000
	 *
	 * Tile data from 8000-8FFF or 8800-97FF
	 * Background tile maps 9800-9BFF or 9C00-9FFF
	 */
	reg [7:0] tiledatahigh [3071:0];
	reg [7:0] tiledatalow [3071:0];
	reg [7:0] bgmap1 [1023:0];
	reg [7:0] bgmap2 [1023:0];
	
	// Upper five bits are Y coord, lower five bits are X coord
	// The new tile number is loaded when vxpos[2:0] is 3'b110
	// The new tile data is loaded when vxpos[2:0] is 3'b111
	// The new tile data is latched and ready when vxpos[2:0] is 3'b000!
	wire [7:0] vxpos_ = vxpos + 1;
	wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};
	reg [7:0] tileno;
	wire [10:0] tileaddr = {tileno, vypos[2:0]};
	reg [7:0] tilehigh, tilelow;
	wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
	assign pixdata = {rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
	
	wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
	wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);

	wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
	wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
	
	always @(negedge clk)
		if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
			tileno <= bgmap1[bgmapaddr_in];
			if (wr && decode_bgmap1 && ~vraminuse)
				bgmap1[bgmapaddr_in] <= data;
		end
	
	always @(negedge clk)
		if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
			tilehigh <= tiledatahigh[tileaddr_in];
			tilelow <= tiledatalow[tileaddr_in];
			if (wr && addr[0] && decode_tiledata && ~vraminuse)
				tiledatahigh[tileaddr_in] <= data;
			if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
				tiledatalow[tileaddr_in] <= data;
		end
  
	/***** Bus interface *****/
	assign data = rd ?
			((addr == `ADDR_LCDC) ? rLCDC :
			 (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
			 (addr == `ADDR_SCY) ? rSCY :
			 (addr == `ADDR_SCX) ? rSCX :
			 (addr == `ADDR_LY) ? posy :
			 (addr == `ADDR_LYC) ? rLYC :
			 (addr == `ADDR_BGP) ? rBGP :
			 (addr == `ADDR_OBP0) ? rOBP0 :
			 (addr == `ADDR_OBP1) ? rOBP1 :
			 (addr == `ADDR_WY) ? rWY :
			 (addr == `ADDR_WX) ? rWX :
			 (decode_tiledata && addr[0]) ? tilehigh :
			 (decode_tiledata && ~addr[0]) ? tilelow :
			 (decode_bgmap1) ? tileno :
			 8'bzzzzzzzz) :
		8'bzzzzzzzz;
  
	always @(negedge clk)
	begin
		if (wr)
			case (addr)
			`ADDR_LCDC:	rLCDC <= data;
			`ADDR_STAT:	rSTAT <= {data[7:2],rSTAT[1:0]};
			`ADDR_SCY:	rSCY <= data;
			`ADDR_SCX:	rSCX <= data;
			`ADDR_LYC:	rLYC <= data;
			`ADDR_DMA:	rDMA <= data;
			`ADDR_BGP:	rBGP <= data;
			`ADDR_OBP0:	rOBP0 <= data;
			`ADDR_OBP1:	rOBP1 <= data;
			`ADDR_WY:	rWY <= data;
			`ADDR_WX:	rWX <= data;
			endcase
	end
endmodule