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[fpgaboy.git] / Buttons.v
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45d9d1c6 1`define ADDR_P1 16'hFF00
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2
3/* note: buttons are 'pressed' when the input is high */
4
5module Buttons(
6 input core_clk,
7 input wr,
8 input rd,
9 input [15:0] addr,
10 inout [7:0] data,
a6b499da 11 input [7:0] buttons,
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12 output reg int
13 );
14
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15 reg rdlatch;
16 reg [15:0] addrlatch;
17
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18 reg [7:0] p1;
19 reg [3:0] oldp1013;
20
a6b499da 21 assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
47a8eefe 22
45d9d1c6 23 wire [3:0] p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) & (p1[5] ? 4'b1111 : ~buttons[7:4]);
47a8eefe 24
a6b499da 25 always @ (posedge core_clk) begin
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26 if(wr) begin
27 case(addr)
28 `ADDR_P1: p1[5:4] <= data[5:4];
29 endcase
30 end
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31 rdlatch <= rd;
32 addrlatch <= addr;
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33 p1[3:0] <= p1013;
34 oldp1013 <= p1013;
35 int <= | (oldp1013 & (oldp1013 ^ p1013));
36 end
37endmodule
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