[fpgaboy.git] / core / insn_ld_sp_hl.v

`define INSN_LD_SP_HL		9'b011111001

`ifdef EXECUTE
	`INSN_LD_SP_HL: begin
		case (cycle)
		0:	tmp <= `_H;
		1:	begin
				`EXEC_NEWCYCLE
				`EXEC_INC_PC
				tmp <= `_L;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_SP_HL: begin
		case (cycle)
		0:	`_SPH <= tmp;
		1:	`_SPL <= tmp;
		endcase
	end
`endif
Commit	Line	Data
e7fe9dc2 JW	1	`define INSN_LD_SP_HL 9'b011111001
e7fe9dc2 JW	2
81358c71 JW	3	`ifdef EXECUTE
	4	`INSN_LD_SP_HL: begin
	5	case (cycle)
5c33c5c0	6	0: tmp <= `_H;
81358c71	7	1: begin
5c33c5c0 JW	8	`EXEC_NEWCYCLE
	9	`EXEC_INC_PC
	10	tmp <= `_L;
81358c71 JW	11	end
	12	endcase
	13	end
	14	`endif
	15
	16	`ifdef WRITEBACK
	17	`INSN_LD_SP_HL: begin
	18	case (cycle)
5c33c5c0 JW	19	0: `_SPH <= tmp;
5c33c5c0 JW	20	1: `_SPL <= tmp;
81358c71 JW	21	endcase
	22	end
	23	`endif