[fpgaboy.git] / core / insn_ld_sp_hl.v

`ifdef EXECUTE
	`INSN_LD_SP_HL: begin
		case (cycle)
		0:	tmp <= `_H;
		1:	begin
				`EXEC_NEWCYCLE
				`EXEC_INC_PC
				tmp <= `_L;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_SP_HL: begin
		case (cycle)
		0:	`_SPH <= tmp;
		1:	`_SPL <= tmp;
		endcase
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_LD_SP_HL: begin
	3	case (cycle)
5c33c5c0	4	0: tmp <= `_H;
81358c71	5	1: begin
5c33c5c0 JW	6	`EXEC_NEWCYCLE
	7	`EXEC_INC_PC
	8	tmp <= `_L;
81358c71 JW	9	end
	10	endcase
	11	end
	12	`endif
	13
	14	`ifdef WRITEBACK
	15	`INSN_LD_SP_HL: begin
	16	case (cycle)
5c33c5c0 JW	17	0: `_SPH <= tmp;
5c33c5c0 JW	18	1: `_SPL <= tmp;
81358c71 JW	19	endcase
	20	end
	21	`endif