Add DI/EI delay test. Add LD M, A.

[fpgaboy.git] / insn_ldm_a.v

// If opcode[4], then ld A, x, else ld x, A
// If opcode[1], then ld 16m8, else ld 8m8

`ifdef EXECUTE
	`INSN_LDM_A: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 16'h0001)
			end
		1:	begin
				`EXEC_INC_PC			// we only hit here if 16m8
				`EXEC_READ(`_PC + 16'h0001)
			end
		2:	if (opcode[4])	// LD A,x
				`EXEC_READ(({tmp, tmp2}))
			else
				`EXEC_WRITE(({tmp, tmp2}), `_A)
		3:	begin
				`EXEC_NEWCYCLE
				`EXEC_INC_PC
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LDM_A: begin
		case (cycle)
		0:	if (!opcode[1]) begin
				tmp <= 8'hFF;
				cycle <= 1;	/* Skip cycle 1 */
			end
		1:	tmp2 <= rdata;
		2:	if (opcode[1])
				tmp2 <= rdata;
			else
				tmp <= rdata; 
		3:	if (opcode[4]) `_A <= rdata;
		endcase
	end
`endif