Finish splitting out functions.

[fpgaboy.git] / insn_ret-retcc.v

`ifdef EXECUTE
	`INSN_RET,`INSN_RETCC: begin
		case (cycle)
		0:	begin
				rd <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]};
			end
		1:	begin	// SPECIAL CASE: cycle does NOT increase linearly with ret!
				`EXEC_INC_PC;	// cycle 1 is skipped if we are not retcc
				case (opcode[4:3])
				`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
				`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
				`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
				`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
				endcase
				rd <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]};
			end
		2:	begin
				rd <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
			end
		3:	begin /* twiddle thumbs */ end
		4:	begin
				`EXEC_NEWCYCLE;
				// do NOT increment PC!
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_RET,`INSN_RETCC: begin
		case (cycle)
		0:	if (opcode[0])	// i.e., not RETCC
				cycle <= 1;	// Skip cycle 1; it gets incremented on the next round.
		1:	begin /* Nothing need happen here. */ end
		2:	registers[`REG_PCL] <= rdata;
		3:	registers[`REG_PCH] <= rdata;
		4:	begin
				{registers[`REG_SPH],registers[`REG_SPL]} <=
					{registers[`REG_SPH],registers[`REG_SPL]} + 2;
				if (opcode[4] && opcode[0])	/* RETI */
					ie <= 1;
			end
		endcase
	end
`endif