Set up the bus a little before the clock.

[fpgaboy.git] / insn_ldx_ahl.v

`ifdef EXECUTE
	`INSN_LDx_AHL: begin
		case (cycle)
		0:	if (opcode[3])		// LDx A, (HL)
				`EXEC_READ(`_HL)
			else
				`EXEC_WRITE(`_HL, `_A)
		1:	begin
				`EXEC_NEWCYCLE
				`EXEC_INC_PC
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LDx_AHL: begin
		case (cycle)
		0:	begin /* Type F */ end
		1:	begin
				if (opcode[3])
					`_A <= rdata;
				`_HL <= opcode[4] ? // if set, LDD, else LDI
					(`_HL - 1) :
					(`_HL + 1);
			end
		endcase
	end
`endif