[fpgaboy.git] / insn_ldx_ahl.v

`ifdef EXECUTE
	`INSN_LDx_AHL: begin
		case (cycle)
		0:	begin
				address <= {registers[`REG_H],registers[`REG_L]};
				if (opcode[3]) begin	// LDx A, (HL)
					rd <= 1;
				end else begin
					wr <= 1;
					wdata <= registers[`REG_A];
				end
			end
		1:	begin
				`EXEC_NEWCYCLE;
				`EXEC_INC_PC;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LDx_AHL: begin
		case (cycle)
		0:	begin /* Type F */ end
		1:	begin
				if (opcode[3])
					registers[`REG_A] <= rdata;
				{registers[`REG_H],registers[`REG_L]} <=
					opcode[4] ? // if set, LDD, else LDI
					({registers[`REG_H],registers[`REG_L]} - 1) :
					({registers[`REG_H],registers[`REG_L]} + 1);
			end
		endcase
	end
`endif
Commit	Line	Data
3ad960bd JW	1	`ifdef EXECUTE
	2	`INSN_LDx_AHL: begin
	3	case (cycle)
	4	0: begin
	5	address <= {registers[`REG_H],registers[`REG_L]};
	6	if (opcode[3]) begin // LDx A, (HL)
	7	rd <= 1;
	8	end else begin
	9	wr <= 1;
	10	wdata <= registers[`REG_A];
	11	end
	12	end
	13	1: begin
	14	`EXEC_NEWCYCLE;
	15	`EXEC_INC_PC;
	16	end
	17	endcase
	18	end
	19	`endif
	20
	21	`ifdef WRITEBACK
	22	`INSN_LDx_AHL: begin
	23	case (cycle)
	24	0: begin /* Type F */ end
	25	1: begin
	26	if (opcode[3])
	27	registers[`REG_A] <= rdata;
	28	{registers[`REG_H],registers[`REG_L]} <=
	29	opcode[4] ? // if set, LDD, else LDI
	30	({registers[`REG_H],registers[`REG_L]} - 1) :
	31	({registers[`REG_H],registers[`REG_L]} + 1);
	32	end
	33	endcase
	34	end
	35	`endif