[fpgaboy.git] / core / insn_ld_reg_imm16.v

`ifdef EXECUTE
	`INSN_LD_reg_imm16: begin
		`EXEC_INC_PC
		case (cycle)
		0:	`EXEC_READ(`_PC + 1)
		1:	`EXEC_READ(`_PC + 1)
		2:	`EXEC_NEWCYCLE
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_reg_imm16: begin
		case (cycle)
		0:	begin /* */ end
		1:	begin
				case (opcode[5:4])
				`INSN_reg16_BC:	`_C <= rdata;
				`INSN_reg16_DE:	`_E <= rdata;
				`INSN_reg16_HL:	`_L <= rdata;
				`INSN_reg16_SP:	`_SPL <= rdata;
				endcase
			end
		2:	begin
				case (opcode[5:4])
				`INSN_reg16_BC:	`_B <= rdata;
				`INSN_reg16_DE:	`_D <= rdata;
				`INSN_reg16_HL:	`_H <= rdata;
				`INSN_reg16_SP:	`_SPH <= rdata;
				endcase
			end
		endcase
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
81358c71 JW	2	`INSN_LD_reg_imm16: begin
5c33c5c0	3	`EXEC_INC_PC
81358c71	4	case (cycle)
5c33c5c0 JW	5	0: `EXEC_READ(`_PC + 1)
	6	1: `EXEC_READ(`_PC + 1)
	7	2: `EXEC_NEWCYCLE
81358c71 JW	8	endcase
	9	end
	10	`endif
	11
	12	`ifdef WRITEBACK
	13	`INSN_LD_reg_imm16: begin
	14	case (cycle)
	15	0: begin /* */ end
	16	1: begin
	17	case (opcode[5:4])
5c33c5c0 JW	18	`INSN_reg16_BC: `_C <= rdata;
	19	`INSN_reg16_DE: `_E <= rdata;
	20	`INSN_reg16_HL: `_L <= rdata;
	21	`INSN_reg16_SP: `_SPL <= rdata;
81358c71 JW	22	endcase
	23	end
	24	2: begin
	25	case (opcode[5:4])
5c33c5c0 JW	26	`INSN_reg16_BC: `_B <= rdata;
	27	`INSN_reg16_DE: `_D <= rdata;
	28	`INSN_reg16_HL: `_H <= rdata;
	29	`INSN_reg16_SP: `_SPH <= rdata;
81358c71 JW	30	endcase
	31	end
	32	endcase
	33	end
	34	`endif