[fpgaboy.git] / insn_ld_reg_imm16.v

`ifdef EXECUTE
	`INSN_LD_reg_imm16: begin
		`EXEC_INC_PC;
		case (cycle)
		0:	begin
				`EXEC_NEXTADDR_PCINC;
				rd <= 1;
			end
		1:	begin
				`EXEC_NEXTADDR_PCINC;
				rd <= 1;
			end
		2:	begin `EXEC_NEWCYCLE; end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_reg_imm16: begin
		case (cycle)
		0:	begin /* */ end
		1:	begin
				case (opcode[5:4])
				`INSN_reg16_BC:	registers[`REG_C] <= rdata;
				`INSN_reg16_DE:	registers[`REG_E] <= rdata;
				`INSN_reg16_HL:	registers[`REG_L] <= rdata;
				`INSN_reg16_SP:	registers[`REG_SPL] <= rdata;
				endcase
			end
		2:	begin
				case (opcode[5:4])
				`INSN_reg16_BC:	registers[`REG_B] <= rdata;
				`INSN_reg16_DE:	registers[`REG_D] <= rdata;
				`INSN_reg16_HL:	registers[`REG_H] <= rdata;
				`INSN_reg16_SP:	registers[`REG_SPH] <= rdata;
				endcase
			end
		endcase
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_LD_reg_imm16: begin
	3	`EXEC_INC_PC;
	4	case (cycle)
	5	0: begin
	6	`EXEC_NEXTADDR_PCINC;
	7	rd <= 1;
	8	end
	9	1: begin
	10	`EXEC_NEXTADDR_PCINC;
	11	rd <= 1;
	12	end
	13	2: begin `EXEC_NEWCYCLE; end
	14	endcase
	15	end
	16	`endif
	17
	18	`ifdef WRITEBACK
	19	`INSN_LD_reg_imm16: begin
	20	case (cycle)
	21	0: begin /* */ end
	22	1: begin
	23	case (opcode[5:4])
	24	`INSN_reg16_BC: registers[`REG_C] <= rdata;
	25	`INSN_reg16_DE: registers[`REG_E] <= rdata;
	26	`INSN_reg16_HL: registers[`REG_L] <= rdata;
	27	`INSN_reg16_SP: registers[`REG_SPL] <= rdata;
	28	endcase
	29	end
	30	2: begin
	31	case (opcode[5:4])
	32	`INSN_reg16_BC: registers[`REG_B] <= rdata;
	33	`INSN_reg16_DE: registers[`REG_D] <= rdata;
	34	`INSN_reg16_HL: registers[`REG_H] <= rdata;
	35	`INSN_reg16_SP: registers[`REG_SPH] <= rdata;
	36	endcase
	37	end
	38	endcase
	39	end
	40	`endif