[fpgaboy.git] / core / insn_ld_reg_imm8.v

`define INSN_LD_reg_imm8	9'b000xxx110

`ifdef EXECUTE
	`INSN_LD_reg_imm8: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 1)
			end
		1:	begin
				`EXEC_INC_PC
				if (opcode[5:3] == `INSN_reg_dHL)
					`EXEC_WRITE(`_HL, rdata)
				else
					`EXEC_NEWCYCLE
			end
		2:	`EXEC_NEWCYCLE
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_reg_imm8:
		case (cycle)
		0:	begin end
		1:	case (opcode[5:3])
			`INSN_reg_A:	begin `_A <= rdata; end
			`INSN_reg_B:	begin `_B <= rdata; end
			`INSN_reg_C:	begin `_C <= rdata; end
			`INSN_reg_D:	begin `_D <= rdata; end
			`INSN_reg_E:	begin `_E <= rdata; end
			`INSN_reg_H:	begin `_H <= rdata; end
			`INSN_reg_L:	begin `_L <= rdata; end
			`INSN_reg_dHL:	begin /* Go off to cycle 2 */ end
			endcase
		2:	begin end
		endcase
`endif
Commit	Line	Data
e7fe9dc2 JW	1	`define INSN_LD_reg_imm8 9'b000xxx110
e7fe9dc2 JW	2
81358c71 JW	3	`ifdef EXECUTE
	4	`INSN_LD_reg_imm8: begin
	5	case (cycle)
	6	0: begin
5c33c5c0 JW	7	`EXEC_INC_PC
5c33c5c0 JW	8	`EXEC_READ(`_PC + 1)
81358c71 JW	9	end
81358c71 JW	10	1: begin
5c33c5c0 JW	11	`EXEC_INC_PC
	12	if (opcode[5:3] == `INSN_reg_dHL)
	13	`EXEC_WRITE(`_HL, rdata)
	14	else
	15	`EXEC_NEWCYCLE
81358c71	16	end
5c33c5c0	17	2: `EXEC_NEWCYCLE
81358c71 JW	18	endcase
	19	end
	20	`endif
	21
	22	`ifdef WRITEBACK
	23	`INSN_LD_reg_imm8:
	24	case (cycle)
	25	0: begin end
	26	1: case (opcode[5:3])
5c33c5c0 JW	27	`INSN_reg_A: begin `_A <= rdata; end
	28	`INSN_reg_B: begin `_B <= rdata; end
	29	`INSN_reg_C: begin `_C <= rdata; end
	30	`INSN_reg_D: begin `_D <= rdata; end
	31	`INSN_reg_E: begin `_E <= rdata; end
	32	`INSN_reg_H: begin `_H <= rdata; end
	33	`INSN_reg_L: begin `_L <= rdata; end
81358c71 JW	34	`INSN_reg_dHL: begin /* Go off to cycle 2 */ end
	35	endcase
	36	2: begin end
	37	endcase
	38	`endif