Move the core to core/

[fpgaboy.git] / core / insn_ld_reg_imm8.v

`ifdef EXECUTE
	`INSN_LD_reg_imm8: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 1)
			end
		1:	begin
				`EXEC_INC_PC
				if (opcode[5:3] == `INSN_reg_dHL)
					`EXEC_WRITE(`_HL, rdata)
				else
					`EXEC_NEWCYCLE
			end
		2:	`EXEC_NEWCYCLE
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_reg_imm8:
		case (cycle)
		0:	begin end
		1:	case (opcode[5:3])
			`INSN_reg_A:	begin `_A <= rdata; end
			`INSN_reg_B:	begin `_B <= rdata; end
			`INSN_reg_C:	begin `_C <= rdata; end
			`INSN_reg_D:	begin `_D <= rdata; end
			`INSN_reg_E:	begin `_E <= rdata; end
			`INSN_reg_H:	begin `_H <= rdata; end
			`INSN_reg_L:	begin `_L <= rdata; end
			`INSN_reg_dHL:	begin /* Go off to cycle 2 */ end
			endcase
		2:	begin end
		endcase
`endif