]> Joshua Wise's Git repositories - fpgaboy.git/blame - CoreTop.prj
Ethernet TX support
[fpgaboy.git] / CoreTop.prj
CommitLineData
4a393852
JW
1verilog work "Uart.v"
2verilog work "Timer.v"
3verilog work "Interrupt.v"
b057a5d6 4verilog work "core/GBZ80Core.v"
4a393852
JW
5verilog work "CPUDCM.v"
6verilog work "7seg.v"
7verilog work "System.v"
8verilog work "LCDC.v"
9verilog work "Framebuffer.v"
6ba4cfea
JW
10verilog work "pixDCM.v"
11verilog work "Sound1.v"
12verilog work "Sound2.v"
13verilog work "Soundcore.v"
a6b499da 14verilog work "Buttons.v"
bc75fc67 15verilog work "PS2Button.v"
99b96879
JW
16verilog work "Ethernet.v"
17verilog work "ethDCM.v"
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