]> Joshua Wise's Git repositories - fpgaboy.git/blame - CoreTop.prj
Add cut 1 of a cellram module
[fpgaboy.git] / CoreTop.prj
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JW
1verilog work "Uart.v"
2verilog work "Timer.v"
3verilog work "Interrupt.v"
4verilog work "GBZ80Core.v"
5verilog work "CPUDCM.v"
6verilog work "7seg.v"
7verilog work "System.v"
8verilog work "LCDC.v"
9verilog work "Framebuffer.v"
6ba4cfea
JW
10verilog work "pixDCM.v"
11verilog work "Sound1.v"
12verilog work "Sound2.v"
13verilog work "Soundcore.v"
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