First attempt at fixing DAA. Add ld (nn), sp.
[fpgaboy.git] / PS2Button.v
CommitLineData
6306dc0a 1module PS2Button(
b057a5d6 2 input clk,
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3 input inclk,
4 input indata,
bc75fc67 5 output wire [7:0] buttons
6306dc0a
CZL
6 );
7
bc75fc67
JW
8 reg [3:0] bitcount = 0;
9 reg [7:0] key = 0;
10 reg keyarrow = 0, keyup = 0, parity = 0;
11 reg key_a = 0,key_b = 0,key_st = 0,key_sel = 0,key_up = 0,key_dn = 0,key_l = 0,key_r = 0;
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12
13 assign buttons = {key_st,key_sel,key_b,key_a,key_dn,key_up,key_l,key_r};
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14
15 /* Clock debouncing */
16 reg lastinclk = 0;
17 reg [5:0] debounce = 0;
18 reg fixedclk = 0;
19 reg [9:0] resetcountdown = 0;
20
21 always @(posedge clk) begin
22 if (inclk != lastinclk) begin
23 lastinclk <= inclk;
24 debounce <= 1;
25 resetcountdown <= 10'b1111111111;
26 end else if (debounce == 0) begin
27 fixedclk <= inclk;
28 resetcountdown <= resetcountdown - 1;
29 end else
30 debounce <= debounce + 1;
31 end
6306dc0a 32
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33 always @(negedge fixedclk) begin
34 if (resetcountdown == 0)
35 bitcount <= 0;
36 else if (bitcount == 10) begin
6306dc0a 37 bitcount <= 0;
77ab69d7 38 if(parity != (^ key)) begin
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CZL
39 if(keyarrow) begin
40 keyarrow <= 0;
41 case(key)
42 8'hF0: keyup <= 1;
43 8'h75: key_up <= 1;
44 8'h74: key_r <= 1;
45 8'h72: key_dn <= 1;
46 8'h6B: key_l <= 1;
47 endcase
48 end
49 else begin
50 if(keyup) begin
51 keyup <= 0;
52 case(key)
53 8'h75: key_up <= 0;
54 8'h74: key_r <= 0;
55 8'h72: key_dn <= 0;
56 8'h6B: key_l <= 0;
57 8'h1C: key_a <= 0;
58 8'h1B: key_b <= 0;
59 8'h5A: key_st <= 0;
60 8'h59: key_sel <= 0;
61 endcase
62 end
63 else begin
64 case(key)
65 8'hE0: keyarrow <= 1;
66 8'hF0: keyup <= 1;
67 8'h1C: key_a <= 1;
68 8'h1B: key_b <= 1;
69 8'h5A: key_st <= 1;
70 8'h59: key_sel <= 1;
71 endcase
72 end
73 end
74 end
75 else begin
76 keyarrow <= 0;
77 keyup <= 0;
78 {key_a,key_b,key_st,key_sel,key_up,key_dn,key_l,key_r} <= 8'b0;
79 end
80 end else
81 bitcount <= bitcount + 1;
82
83 case(bitcount)
84 1: key[0] <= indata;
85 2: key[1] <= indata;
86 3: key[2] <= indata;
87 4: key[3] <= indata;
88 5: key[4] <= indata;
89 6: key[5] <= indata;
90 7: key[6] <= indata;
91 8: key[7] <= indata;
92 9: parity <= indata;
93 endcase
94 end
95
96endmodule
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