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6306dc0a CZL |
1 | module PS2Button( |
2 | input inclk, | |
3 | input indata, | |
bc75fc67 | 4 | output wire [7:0] buttons |
6306dc0a CZL |
5 | ); |
6 | ||
bc75fc67 JW |
7 | reg [3:0] bitcount = 0; |
8 | reg [7:0] key = 0; | |
9 | reg keyarrow = 0, keyup = 0, parity = 0; | |
10 | reg key_a = 0,key_b = 0,key_st = 0,key_sel = 0,key_up = 0,key_dn = 0,key_l = 0,key_r = 0; | |
6306dc0a CZL |
11 | |
12 | assign buttons = {key_st,key_sel,key_b,key_a,key_dn,key_up,key_l,key_r}; | |
13 | ||
14 | always @ (negedge inclk) begin | |
15 | if(bitcount == 10) begin | |
16 | bitcount <= 0; | |
77ab69d7 | 17 | if(parity != (^ key)) begin |
6306dc0a CZL |
18 | if(keyarrow) begin |
19 | keyarrow <= 0; | |
20 | case(key) | |
21 | 8'hF0: keyup <= 1; | |
22 | 8'h75: key_up <= 1; | |
23 | 8'h74: key_r <= 1; | |
24 | 8'h72: key_dn <= 1; | |
25 | 8'h6B: key_l <= 1; | |
26 | endcase | |
27 | end | |
28 | else begin | |
29 | if(keyup) begin | |
30 | keyup <= 0; | |
31 | case(key) | |
32 | 8'h75: key_up <= 0; | |
33 | 8'h74: key_r <= 0; | |
34 | 8'h72: key_dn <= 0; | |
35 | 8'h6B: key_l <= 0; | |
36 | 8'h1C: key_a <= 0; | |
37 | 8'h1B: key_b <= 0; | |
38 | 8'h5A: key_st <= 0; | |
39 | 8'h59: key_sel <= 0; | |
40 | endcase | |
41 | end | |
42 | else begin | |
43 | case(key) | |
44 | 8'hE0: keyarrow <= 1; | |
45 | 8'hF0: keyup <= 1; | |
46 | 8'h1C: key_a <= 1; | |
47 | 8'h1B: key_b <= 1; | |
48 | 8'h5A: key_st <= 1; | |
49 | 8'h59: key_sel <= 1; | |
50 | endcase | |
51 | end | |
52 | end | |
53 | end | |
54 | else begin | |
55 | keyarrow <= 0; | |
56 | keyup <= 0; | |
57 | {key_a,key_b,key_st,key_sel,key_up,key_dn,key_l,key_r} <= 8'b0; | |
58 | end | |
59 | end else | |
60 | bitcount <= bitcount + 1; | |
61 | ||
62 | case(bitcount) | |
63 | 1: key[0] <= indata; | |
64 | 2: key[1] <= indata; | |
65 | 3: key[2] <= indata; | |
66 | 4: key[3] <= indata; | |
67 | 5: key[4] <= indata; | |
68 | 6: key[5] <= indata; | |
69 | 7: key[6] <= indata; | |
70 | 8: key[7] <= indata; | |
71 | 9: parity <= indata; | |
72 | endcase | |
73 | end | |
74 | ||
75 | endmodule |