[fpgaboy.git] / insn_rst.v

`ifdef EXECUTE
	`INSN_RST: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC;		// This goes FIRST in RST
			end
		1:	begin
				wr <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
				wdata <= registers[`REG_PCH];
			end
		2:	begin
				wr <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
				wdata <= registers[`REG_PCL];
			end
		3:	begin
				`EXEC_NEWCYCLE;
				{registers[`REG_PCH],registers[`REG_PCL]} <=
					{10'b0,opcode[5:3],3'b0};
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_RST: begin
		case (cycle)
		0:	begin /* type F */ end
		1:	begin /* type F */ end
		2:	begin /* type F */ end
		3:	{registers[`REG_SPH],registers[`REG_SPL]} <=
				{registers[`REG_SPH],registers[`REG_SPL]}-2;
		endcase
	end
`endif
Commit	Line	Data
df770340 JW	1	`ifdef EXECUTE
	2	`INSN_RST: begin
	3	case (cycle)
	4	0: begin
	5	`EXEC_INC_PC; // This goes FIRST in RST
	6	end
	7	1: begin
	8	wr <= 1;
	9	address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
	10	wdata <= registers[`REG_PCH];
	11	end
	12	2: begin
	13	wr <= 1;
	14	address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
	15	wdata <= registers[`REG_PCL];
	16	end
	17	3: begin
	18	`EXEC_NEWCYCLE;
	19	{registers[`REG_PCH],registers[`REG_PCL]} <=
	20	{10'b0,opcode[5:3],3'b0};
	21	end
	22	endcase
	23	end
	24	`endif
	25
	26	`ifdef WRITEBACK
	27	`INSN_RST: begin
	28	case (cycle)
	29	0: begin /* type F */ end
	30	1: begin /* type F */ end
	31	2: begin /* type F */ end
	32	3: {registers[`REG_SPH],registers[`REG_SPL]} <=
	33	{registers[`REG_SPH],registers[`REG_SPL]}-2;
	34	endcase
	35	end
	36	`endif