[fpgaboy.git] / insn_push_reg.v

`ifdef EXECUTE
	`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
		case (cycle)
		0:	begin
				wr <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
				case (opcode[5:4])
				`INSN_stack_AF:	wdata <= registers[`REG_A];
				`INSN_stack_BC:	wdata <= registers[`REG_B];
				`INSN_stack_DE:	wdata <= registers[`REG_D];
				`INSN_stack_HL:	wdata <= registers[`REG_H];
				endcase
			end
		1:	begin
				wr <= 1;
				address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
				case (opcode[5:4])
				`INSN_stack_AF:	wdata <= registers[`REG_F];
				`INSN_stack_BC:	wdata <= registers[`REG_C];
				`INSN_stack_DE:	wdata <= registers[`REG_E];
				`INSN_stack_HL:	wdata <= registers[`REG_L];
				endcase
			end
		2:	begin /* Twiddle thumbs. */ end
		3:	begin
				`EXEC_NEWCYCLE;
				`EXEC_INC_PC;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
		case (cycle)
		0:	begin /* type F */ end
		1:	begin /* type F */ end
		2:	begin /* type F */ end
		3:	{registers[`REG_SPH],registers[`REG_SPL]} <=
				{registers[`REG_SPH],registers[`REG_SPL]} - 2;
		endcase
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
	3	case (cycle)
	4	0: begin
	5	wr <= 1;
	6	address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
	7	case (opcode[5:4])
	8	`INSN_stack_AF: wdata <= registers[`REG_A];
	9	`INSN_stack_BC: wdata <= registers[`REG_B];
	10	`INSN_stack_DE: wdata <= registers[`REG_D];
	11	`INSN_stack_HL: wdata <= registers[`REG_H];
	12	endcase
	13	end
	14	1: begin
	15	wr <= 1;
	16	address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
	17	case (opcode[5:4])
	18	`INSN_stack_AF: wdata <= registers[`REG_F];
	19	`INSN_stack_BC: wdata <= registers[`REG_C];
	20	`INSN_stack_DE: wdata <= registers[`REG_E];
	21	`INSN_stack_HL: wdata <= registers[`REG_L];
	22	endcase
	23	end
	24	2: begin /* Twiddle thumbs. */ end
	25	3: begin
	26	`EXEC_NEWCYCLE;
	27	`EXEC_INC_PC;
	28	end
	29	endcase
	30	end
	31	`endif
	32
	33	`ifdef WRITEBACK
	34	`INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
	35	case (cycle)
	36	0: begin /* type F */ end
	37	1: begin /* type F */ end
	38	2: begin /* type F */ end
	39	3: {registers[`REG_SPH],registers[`REG_SPL]} <=
	40	{registers[`REG_SPH],registers[`REG_SPL]} - 2;
	41	endcase
	42	end
	43	`endif