Add mock up LCDC
[fpgaboy.git] / opcodes
CommitLineData
f9000d73
JW
1YET UNIMPLEMENTED:
2
3imm3 = 3-bit immediate value in 8 bits
4imm8 = 8-bit immediate value
5imm16 = 16-bit immediate value
616m8 = 8-bit value at the 16-bit address
78m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
8
9bits insn notes
100000 0010 LD (BC), A
110000 1000 LD 16m16,SP loads SP
120000 1001 ADD HL, BC
130000 1010 LD A, (BC)
140001 0000 STOP
150001 0010 LD (DE), A
160001 1001 ADD HL, DE
170001 1010 LD A, (DE)
180010 1001 ADD HL, HL
190011 1001 ADD HL, SP
200111 0110 HALT Danger! Helvetica!
211100 1011 - - - see two-byte opcodes below
221110 1000 ADD SP, imm8
231111 1000 LDHL SP, imm8 load SP+n (signed n) into HL
24
25*****************************
26
27fucking two-byte opcodes
28
29bits insn notes
301100 1011 0000 0000 RLC B
311100 1011 0000 0001 RLC C
321100 1011 0000 0010 RLC D
331100 1011 0000 0011 RLC E
341100 1011 0000 0100 RLC H
351100 1011 0000 0101 RLC L
361100 1011 0000 0110 RLC (HL)
371100 1011 0000 0111 RLC A
38
391100 1011 0000 1000 RRC B
401100 1011 0000 1001 RRC C
411100 1011 0000 1010 RRC D
421100 1011 0000 1011 RRC E
431100 1011 0000 1100 RRC H
441100 1011 0000 1101 RRC L
451100 1011 0000 1110 RRC (HL)
461100 1011 0000 1111 RRC A
47
481100 1011 0001 0000 RL B
491100 1011 0001 0001 RL C
501100 1011 0001 0010 RL D
511100 1011 0001 0011 RL E
521100 1011 0001 0100 RL H
531100 1011 0001 0101 RL L
541100 1011 0001 0110 RL (HL)
551100 1011 0001 0111 RL A
56
571100 1011 0001 1000 RR B
581100 1011 0001 1001 RR C
591100 1011 0001 1010 RR D
601100 1011 0001 1011 RR E
611100 1011 0001 1100 RR H
621100 1011 0001 1101 RR L
631100 1011 0001 1110 RR (HL)
641100 1011 0001 1111 RR A
65
661100 1011 0010 0000 SLA B
671100 1011 0010 0001 SLA C
681100 1011 0010 0010 SLA D
691100 1011 0010 0011 SLA E
701100 1011 0010 0100 SLA H
711100 1011 0010 0101 SLA L
721100 1011 0010 0110 SLA (HL)
731100 1011 0010 0111 SLA A
74
751100 1011 0010 1000 SRA B
761100 1011 0010 1001 SRA C
771100 1011 0010 1010 SRA D
781100 1011 0010 1011 SRA E
791100 1011 0010 1100 SRA H
801100 1011 0010 1101 SRA L
811100 1011 0010 1110 SRA (HL)
821100 1011 0010 1111 SRA A
83
841100 1011 0011 1000 SRL B
851100 1011 0011 1001 SRL C
861100 1011 0011 1010 SRL D
871100 1011 0011 1011 SRL E
881100 1011 0011 1100 SRL H
891100 1011 0011 1101 SRL L
901100 1011 0011 1110 SRL (HL)
911100 1011 0011 1111 SRL A
92
931100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte
941100 1011 0011 0001 SWAP C
951100 1011 0011 0010 SWAP D
961100 1011 0011 0011 SWAP E
971100 1011 0011 0100 SWAP H
981100 1011 0011 0101 SWAP L
991100 1011 0011 0110 SWAP (HL)
1001100 1011 0011 0111 SWAP A
101
1021100 1011 0100 0000 BIT imm3, B test bit specified by imm3
1031100 1011 0100 0001 BIT imm3, C
1041100 1011 0100 0010 BIT imm3, D
1051100 1011 0100 0011 BIT imm3, E
1061100 1011 0100 0100 BIT imm3, H
1071100 1011 0100 0101 BIT imm3, L
1081100 1011 0100 0110 BIT imm3, (HL)
1091100 1011 0100 0111 BIT imm3, A
110
1111100 1011 1000 0000 RES imm3, B reset bit specified by imm3
1121100 1011 1000 0001 RES imm3, C
1131100 1011 1000 0010 RES imm3, D
1141100 1011 1000 0011 RES imm3, E
1151100 1011 1000 0100 RES imm3, H
1161100 1011 1000 0101 RES imm3, L
1171100 1011 1000 0110 RES imm3, (HL)
1181100 1011 1000 0111 RES imm3, A
119
1201100 1011 1100 0000 SET imm3, B set bit specified by imm3
1211100 1011 1100 0001 SET imm3, C
1221100 1011 1100 0010 SET imm3, D
1231100 1011 1100 0011 SET imm3, E
1241100 1011 1100 0100 SET imm3, H
1251100 1011 1100 0101 SET imm3, L
1261100 1011 1100 0110 SET imm3, (HL)
1271100 1011 1100 0111 SET imm3, A
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