RAM needs to be writable, I guess

[fpgaboy.git] / core / insn_push_reg.v

`define INSN_PUSH_reg		9'b011xx0101

`ifdef EXECUTE
	`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
		case (cycle)
		0:	case (opcode[5:4])
			`INSN_stack_AF:	`EXEC_WRITE(`_SP - 1, `_A)
			`INSN_stack_BC:	`EXEC_WRITE(`_SP - 1, `_B)
			`INSN_stack_DE:	`EXEC_WRITE(`_SP - 1, `_D)
			`INSN_stack_HL:	`EXEC_WRITE(`_SP - 1, `_H)
			endcase
		1:	case (opcode[5:4])
			`INSN_stack_AF:	`EXEC_WRITE(`_SP - 2, `_F)
			`INSN_stack_BC:	`EXEC_WRITE(`_SP - 2, `_C)
			`INSN_stack_DE:	`EXEC_WRITE(`_SP - 2, `_E)
			`INSN_stack_HL:	`EXEC_WRITE(`_SP - 2, `_L)
			endcase
		2:	begin /* Twiddle thumbs. */ end
		3:	begin
				`EXEC_NEWCYCLE
				`EXEC_INC_PC
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_PUSH_reg: begin	/* PUSH is 16 cycles! */
		case (cycle)
		0:	begin /* type F */ end
		1:	begin /* type F */ end
		2:	begin /* type F */ end
		3:	`_SP <= `_SP - 2;
		endcase
	end
`endif