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Commit | Line | Data |
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7541ec17 JW |
1 | VLOGS = 7seg.v Framebuffer.v GBZ80Core.v Interrupt.v LCDC.v Sound1.v \ |
2 | Sound2.v Soundcore.v System.v Timer.v Uart.v | |
3 | ||
4 | VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \ | |
5 | insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v insn_ret-retcc.v \ | |
6 | allinsns.v insn_alu8.v insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v \ | |
7 | insn_ld_reg_imm16.v insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v \ | |
8 | CPUDCM.v insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \ | |
5bac4cf0 | 9 | insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \ |
7541ec17 | 10 | insn_ldm8_a.v insn_ldm16_a.v insn_ldbcde_a.v insn_alu_ext.v \ |
00a4c19f | 11 | insn_bit.v insn_two_byte.v insn_incdec_reg8.v insn_add_hl.v |
9c834ff2 | 12 | |
3db3fc27 | 13 | all: CoreTop.svf |
9c834ff2 | 14 | |
7541ec17 JW |
15 | sim: CoreTop_isim.exe |
16 | ||
49c326da | 17 | CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL) fpgaboot.hex gbboot.hex |
9c834ff2 JW |
18 | xst -ifn CoreTop.xst -ofn CoreTop.syr |
19 | ||
5bac4cf0 | 20 | CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf |
91c74a3f | 21 | ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd |
9c834ff2 JW |
22 | |
23 | CoreTop_map.ncd: CoreTop.ngd | |
24 | map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf | |
25 | ||
26 | CoreTop.ncd: CoreTop_map.ncd | |
27 | par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf | |
28 | ||
29 | CoreTop.twr: CoreTop_map.ncd | |
30 | trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf | |
31 | ||
32 | CoreTop.bit: CoreTop.ut CoreTop.ncd | |
33 | bitgen -f CoreTop.ut CoreTop.ncd | |
7028b02c | 34 | |
179b4347 JW |
35 | netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd |
36 | netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v | |
37 | ||
38 | netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v | |
39 | vlogcomp netgen/par/CoreTop_timesim.v | |
40 | vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v | |
41 | ||
42 | CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work | |
43 | fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl | |
44 | ||
7541ec17 JW |
45 | CoreTop_isim.exe: $(VLOGS_ALL) |
46 | vlogcomp -d isim $(VLOGS) | |
47 | fuse -t CoreTop -o CoreTop_isim.exe | |
48 | ||
179b4347 JW |
49 | parsim: CoreTop_isim_par.exe |
50 | ||
5bac4cf0 JW |
51 | %.o: %.asm |
52 | rgbasm -o$@ $< | |
7028b02c | 53 | |
922655dd | 54 | %.bin: %.o |
5bac4cf0 JW |
55 | echo "[Objects]" > tmp.lnk |
56 | echo $< >> tmp.lnk | |
57 | echo "" >> tmp.lnk | |
58 | echo "[Output]" >> tmp.lnk | |
59 | echo $@ >> tmp.lnk | |
60 | xlink tmp.lnk | |
61 | rm tmp.lnk | |
7028b02c | 62 | |
2b7d78b5 | 63 | %.mem: %.bin mashrom |
5bac4cf0 | 64 | ./mashrom < $< > $@ |
7028b02c | 65 | |
49c326da JW |
66 | fpgaboot.hex: fpgaboot.bin mashrom |
67 | ./mashrom 256 < $< > $@ | |
68 | ||
69 | ||
91c74a3f | 70 | CoreTop.svf: CoreTop.bit impact.cmd |
5bac4cf0 JW |
71 | sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd |
72 | impact -batch tmp.cmd | |
179b4347 JW |
73 | |
74 | parsim: CoreTop | |
75 |