Add some verilator and isim compatibility
[fpgaboy.git] / Makefile
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1VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
2 insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \
3 insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \
4 insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \
5 insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
6 insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
7 insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
4fd47c85 8 Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \
b4f3ac35 9 insn_ldbcde_a.v insn_alu_ext.v insn_bit.v insn_two_byte.v \
6ba4cfea 10 insn_incdec_reg8.v Sound1.v Sound2.v Soundcore.v
9c834ff2 11
6bd4619b 12all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr
9c834ff2 13
6c46357c 14CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS)
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15 xst -ifn CoreTop.xst -ofn CoreTop.syr
16
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17CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
18 ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
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19
20CoreTop_map.ncd: CoreTop.ngd
21 map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
22
23CoreTop.ncd: CoreTop_map.ncd
24 par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf
25
26CoreTop.twr: CoreTop_map.ncd
27 trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf
28
29CoreTop.bit: CoreTop.ut CoreTop.ncd
30 bitgen -f CoreTop.ut CoreTop.ncd
7028b02c 31
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32netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
33 netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
34
35netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
36 vlogcomp netgen/par/CoreTop_timesim.v
37 vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
38
39CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
40 fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
41
42parsim: CoreTop_isim_par.exe
43
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44%.o: %.asm
45 rgbasm -o$@ $<
7028b02c 46
922655dd 47%.bin: %.o
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48 echo "[Objects]" > tmp.lnk
49 echo $< >> tmp.lnk
50 echo "" >> tmp.lnk
51 echo "[Output]" >> tmp.lnk
52 echo $@ >> tmp.lnk
53 xlink tmp.lnk
54 rm tmp.lnk
7028b02c 55
2b7d78b5 56%.mem: %.bin mashrom
5bac4cf0 57 ./mashrom < $< > $@
7028b02c 58
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59CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
60 data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@
7028b02c 61
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62CoreTop_%.svf: CoreTop_%.bit impact.cmd
63 sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
64 impact -batch tmp.cmd
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65
66parsim: CoreTop
67
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