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[fpgaboy.git] / core / insn_ret-retcc.v
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1`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET
2`define INSN_RETCC 9'b0110xx000
3
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4`ifdef EXECUTE
5 `INSN_RET,`INSN_RETCC: begin
6 case (cycle)
5c33c5c0 7 0: `EXEC_READ(`_SP)
df770340 8 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret!
5c33c5c0 9 `EXEC_INC_PC // cycle 1 is skipped if we are not retcc
df770340 10 case (opcode[4:3])
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11 `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE
12 `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE
13 `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE
14 `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE
df770340 15 endcase
5c33c5c0 16 `EXEC_READ(`_SP) // retry the read
df770340 17 end
5c33c5c0 18 2: `EXEC_READ(`_SP + 1)
df770340 19 3: begin /* twiddle thumbs */ end
5c33c5c0 20 4: `EXEC_NEWCYCLE
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21 endcase
22 end
23`endif
24
25`ifdef WRITEBACK
26 `INSN_RET,`INSN_RETCC: begin
27 case (cycle)
28 0: if (opcode[0]) // i.e., not RETCC
29 cycle <= 1; // Skip cycle 1; it gets incremented on the next round.
30 1: begin /* Nothing need happen here. */ end
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31 2: `_PCL <= rdata;
32 3: `_PCH <= rdata;
df770340 33 4: begin
5c33c5c0 34 `_SP <= `_SP + 2;
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35 if (opcode[4] && opcode[0]) /* RETI */
36 ie <= 1;
37 end
38 endcase
39 end
40`endif
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