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[fpgaboy.git] / Makefile
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b057a5d6 1VLOGS = 7seg.v Framebuffer.v core/GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
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2 Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v PS2Button.v \
3 Ethernet.v
7541ec17 4
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5VLOGS_ALL = $(VLOGS) core/insn_call-callcc.v core/insn_incdec16.v \
6 core/insn_jr-jrcc.v core/insn_ld_reg_hl.v core/insn_ld_reg_reg.v \
7 core/insn_nop.v core/insn_ret-retcc.v core/allinsns.v \
8 core/insn_alu8.v core/insn_di-ei.v core/insn_jp_hl.v \
9 core/insn_ldh_ac.v core/insn_ld_reg_imm16.v core/insn_ld_sp_hl.v \
10 core/insn_pop_reg.v core/insn_rst.v CPUDCM.v core/insn_alu_a.v \
11 core/insn_halt.v core/insn_jp-jpcc.v core/insn_ld_hl_reg.v \
12 core/insn_ld_reg_imm8.v core/insn_ldx_ahl.v core/insn_push_reg.v \
13 core/insn_vop_intr.v core/insn_ldm8_a.v core/insn_ldm16_a.v \
14 core/insn_ldbcde_a.v core/insn_alu_ext.v core/insn_bit.v \
84dd189a 15 core/insn_two_byte.v core/insn_incdec_reg8.v core/insn_add_hl.v \
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16 core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v core/insn_ld_nn_sp.v \
17 core/insn_setres.v
9c834ff2 18
3db3fc27 19all: CoreTop.svf
9c834ff2 20
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21sim: CoreTop_isim.exe
22
49c326da 23CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL) fpgaboot.hex gbboot.hex
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24 xst -ifn CoreTop.xst -ofn CoreTop.syr
25
5bac4cf0 26CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
91c74a3f 27 ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
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28
29CoreTop_map.ncd: CoreTop.ngd
30 map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
31
32CoreTop.ncd: CoreTop_map.ncd
33 par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf
34
35CoreTop.twr: CoreTop_map.ncd
36 trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf
37
38CoreTop.bit: CoreTop.ut CoreTop.ncd
39 bitgen -f CoreTop.ut CoreTop.ncd
7028b02c 40
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41netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
42 netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
43
44netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
45 vlogcomp netgen/par/CoreTop_timesim.v
46 vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
47
48CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
49 fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
50
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51CoreTop_isim.exe: $(VLOGS_ALL)
52 vlogcomp -d isim $(VLOGS)
53 fuse -t CoreTop -o CoreTop_isim.exe
54
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55parsim: CoreTop_isim_par.exe
56
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57%.o: %.asm
58 rgbasm -o$@ $<
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922655dd 60%.bin: %.o
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61 echo "[Objects]" > tmp.lnk
62 echo $< >> tmp.lnk
63 echo "" >> tmp.lnk
64 echo "[Output]" >> tmp.lnk
65 echo $@ >> tmp.lnk
66 xlink tmp.lnk
67 rm tmp.lnk
7028b02c 68
2b7d78b5 69%.mem: %.bin mashrom
5bac4cf0 70 ./mashrom < $< > $@
7028b02c 71
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72fpgaboot.hex: fpgaboot.bin mashrom
73 ./mashrom 256 < $< > $@
74
75
91c74a3f 76CoreTop.svf: CoreTop.bit impact.cmd
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77 sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
78 impact -batch tmp.cmd
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79
80parsim: CoreTop
81
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