[fpgaboy.git] / opcodes

YET UNIMPLEMENTED:

imm3  = 3-bit immediate value in 8 bits
imm8  = 8-bit immediate value
imm16 = 16-bit immediate value
16m8  = 8-bit value at the 16-bit address
8m8   = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)

bits         insn                 notes
0000 1000    LD    16m16,SP      loads SP
0000 1001    ADD   HL,   BC
0001 0000    STOP
0001 1001    ADD   HL,   DE
0010 1001    ADD   HL,   HL
0011 1001    ADD   HL,   SP
0111 0110    HALT                 Danger! Helvetica!
1100 1011    -     -     -        see two-byte opcodes below
1110 1000    ADD   SP,   imm8
1111 1000    LDHL  SP,   imm8     load SP+n (signed n) into HL

*****************************

fucking two-byte opcodes

bits                   insn               notes
1100 1011 0000 0000    RLC   B
1100 1011 0000 0001    RLC   C
1100 1011 0000 0010    RLC   D
1100 1011 0000 0011    RLC   E
1100 1011 0000 0100    RLC   H
1100 1011 0000 0101    RLC   L
1100 1011 0000 0110    RLC   (HL)
1100 1011 0000 0111    RLC   A

1100 1011 0000 1000    RRC   B
1100 1011 0000 1001    RRC   C
1100 1011 0000 1010    RRC   D
1100 1011 0000 1011    RRC   E
1100 1011 0000 1100    RRC   H
1100 1011 0000 1101    RRC   L
1100 1011 0000 1110    RRC   (HL)
1100 1011 0000 1111    RRC   A

1100 1011 0001 0000    RL    B
1100 1011 0001 0001    RL    C
1100 1011 0001 0010    RL    D
1100 1011 0001 0011    RL    E
1100 1011 0001 0100    RL    H
1100 1011 0001 0101    RL    L
1100 1011 0001 0110    RL    (HL)
1100 1011 0001 0111    RL    A

1100 1011 0001 1000    RR    B
1100 1011 0001 1001    RR    C
1100 1011 0001 1010    RR    D
1100 1011 0001 1011    RR    E
1100 1011 0001 1100    RR    H
1100 1011 0001 1101    RR    L
1100 1011 0001 1110    RR    (HL)
1100 1011 0001 1111    RR    A

1100 1011 0010 0000    SLA   B
1100 1011 0010 0001    SLA   C
1100 1011 0010 0010    SLA   D
1100 1011 0010 0011    SLA   E
1100 1011 0010 0100    SLA   H
1100 1011 0010 0101    SLA   L
1100 1011 0010 0110    SLA   (HL)
1100 1011 0010 0111    SLA   A

1100 1011 0010 1000    SRA   B
1100 1011 0010 1001    SRA   C
1100 1011 0010 1010    SRA   D
1100 1011 0010 1011    SRA   E
1100 1011 0010 1100    SRA   H
1100 1011 0010 1101    SRA   L
1100 1011 0010 1110    SRA   (HL)
1100 1011 0010 1111    SRA   A

1100 1011 0011 1000    SRL   B
1100 1011 0011 1001    SRL   C
1100 1011 0011 1010    SRL   D
1100 1011 0011 1011    SRL   E
1100 1011 0011 1100    SRL   H
1100 1011 0011 1101    SRL   L
1100 1011 0011 1110    SRL   (HL)
1100 1011 0011 1111    SRL   A

1100 1011 0011 0000    SWAP  B            swaps upper and lower nibbles of a byte
1100 1011 0011 0001    SWAP  C
1100 1011 0011 0010    SWAP  D
1100 1011 0011 0011    SWAP  E
1100 1011 0011 0100    SWAP  H
1100 1011 0011 0101    SWAP  L
1100 1011 0011 0110    SWAP  (HL)
1100 1011 0011 0111    SWAP  A

1100 1011 0100 0000    BIT   imm3, B      test bit specified by imm3
1100 1011 0100 0001    BIT   imm3, C
1100 1011 0100 0010    BIT   imm3, D
1100 1011 0100 0011    BIT   imm3, E
1100 1011 0100 0100    BIT   imm3, H
1100 1011 0100 0101    BIT   imm3, L
1100 1011 0100 0110    BIT   imm3, (HL)
1100 1011 0100 0111    BIT   imm3, A

1100 1011 1000 0000    RES   imm3, B      reset bit specified by imm3
1100 1011 1000 0001    RES   imm3, C
1100 1011 1000 0010    RES   imm3, D
1100 1011 1000 0011    RES   imm3, E
1100 1011 1000 0100    RES   imm3, H
1100 1011 1000 0101    RES   imm3, L
1100 1011 1000 0110    RES   imm3, (HL)
1100 1011 1000 0111    RES   imm3, A

1100 1011 1100 0000    SET   imm3, B      set bit specified by imm3
1100 1011 1100 0001    SET   imm3, C
1100 1011 1100 0010    SET   imm3, D
1100 1011 1100 0011    SET   imm3, E
1100 1011 1100 0100    SET   imm3, H
1100 1011 1100 0101    SET   imm3, L
1100 1011 1100 0110    SET   imm3, (HL)
1100 1011 1100 0111    SET   imm3, A
Commit	Line	Data
f9000d73 JW	1	YET UNIMPLEMENTED:
	2
	3	imm3 = 3-bit immediate value in 8 bits
	4	imm8 = 8-bit immediate value
	5	imm16 = 16-bit immediate value
	6	16m8 = 8-bit value at the 16-bit address
	7	8m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
	8
	9	bits insn notes
f9000d73 JW	10	0000 1000 LD 16m16,SP loads SP
f9000d73 JW	11	0000 1001 ADD HL, BC
f9000d73	12	0001 0000 STOP
f9000d73	13	0001 1001 ADD HL, DE
f9000d73 JW	14	0010 1001 ADD HL, HL
	15	0011 1001 ADD HL, SP
	16	0111 0110 HALT Danger! Helvetica!
	17	1100 1011 - - - see two-byte opcodes below
	18	1110 1000 ADD SP, imm8
	19	1111 1000 LDHL SP, imm8 load SP+n (signed n) into HL
	20
	21	*****************************
	22
	23	fucking two-byte opcodes
	24
	25	bits insn notes
	26	1100 1011 0000 0000 RLC B
	27	1100 1011 0000 0001 RLC C
	28	1100 1011 0000 0010 RLC D
	29	1100 1011 0000 0011 RLC E
	30	1100 1011 0000 0100 RLC H
	31	1100 1011 0000 0101 RLC L
	32	1100 1011 0000 0110 RLC (HL)
	33	1100 1011 0000 0111 RLC A
	34
	35	1100 1011 0000 1000 RRC B
	36	1100 1011 0000 1001 RRC C
	37	1100 1011 0000 1010 RRC D
	38	1100 1011 0000 1011 RRC E
	39	1100 1011 0000 1100 RRC H
	40	1100 1011 0000 1101 RRC L
	41	1100 1011 0000 1110 RRC (HL)
	42	1100 1011 0000 1111 RRC A
	43
	44	1100 1011 0001 0000 RL B
	45	1100 1011 0001 0001 RL C
	46	1100 1011 0001 0010 RL D
	47	1100 1011 0001 0011 RL E
	48	1100 1011 0001 0100 RL H
	49	1100 1011 0001 0101 RL L
	50	1100 1011 0001 0110 RL (HL)
	51	1100 1011 0001 0111 RL A
	52
	53	1100 1011 0001 1000 RR B
	54	1100 1011 0001 1001 RR C
	55	1100 1011 0001 1010 RR D
	56	1100 1011 0001 1011 RR E
	57	1100 1011 0001 1100 RR H
	58	1100 1011 0001 1101 RR L
	59	1100 1011 0001 1110 RR (HL)
	60	1100 1011 0001 1111 RR A
	61
	62	1100 1011 0010 0000 SLA B
	63	1100 1011 0010 0001 SLA C
	64	1100 1011 0010 0010 SLA D
	65	1100 1011 0010 0011 SLA E
	66	1100 1011 0010 0100 SLA H
	67	1100 1011 0010 0101 SLA L
	68	1100 1011 0010 0110 SLA (HL)
	69	1100 1011 0010 0111 SLA A
	70
	71	1100 1011 0010 1000 SRA B
	72	1100 1011 0010 1001 SRA C
	73	1100 1011 0010 1010 SRA D
	74	1100 1011 0010 1011 SRA E
	75	1100 1011 0010 1100 SRA H
	76	1100 1011 0010 1101 SRA L
	77	1100 1011 0010 1110 SRA (HL)
78	1100 1011 0010 1111 SRA A
79
80	1100 1011 0011 1000 SRL B
81	1100 1011 0011 1001 SRL C
82	1100 1011 0011 1010 SRL D
83	1100 1011 0011 1011 SRL E
84	1100 1011 0011 1100 SRL H
85	1100 1011 0011 1101 SRL L
86	1100 1011 0011 1110 SRL (HL)
87	1100 1011 0011 1111 SRL A
88
89	1100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte
90	1100 1011 0011 0001 SWAP C
91	1100 1011 0011 0010 SWAP D
92	1100 1011 0011 0011 SWAP E
93	1100 1011 0011 0100 SWAP H
94	1100 1011 0011 0101 SWAP L
95	1100 1011 0011 0110 SWAP (HL)
96	1100 1011 0011 0111 SWAP A
97
98	1100 1011 0100 0000 BIT imm3, B test bit specified by imm3
99	1100 1011 0100 0001 BIT imm3, C
100	1100 1011 0100 0010 BIT imm3, D
101	1100 1011 0100 0011 BIT imm3, E
102	1100 1011 0100 0100 BIT imm3, H
103	1100 1011 0100 0101 BIT imm3, L
104	1100 1011 0100 0110 BIT imm3, (HL)
105	1100 1011 0100 0111 BIT imm3, A
106
107	1100 1011 1000 0000 RES imm3, B reset bit specified by imm3
108	1100 1011 1000 0001 RES imm3, C
109	1100 1011 1000 0010 RES imm3, D
110	1100 1011 1000 0011 RES imm3, E
111	1100 1011 1000 0100 RES imm3, H
112	1100 1011 1000 0101 RES imm3, L
113	1100 1011 1000 0110 RES imm3, (HL)
114	1100 1011 1000 0111 RES imm3, A
115
116	1100 1011 1100 0000 SET imm3, B set bit specified by imm3
117	1100 1011 1100 0001 SET imm3, C
118	1100 1011 1100 0010 SET imm3, D
119	1100 1011 1100 0011 SET imm3, E
120	1100 1011 1100 0100 SET imm3, H
121	1100 1011 1100 0101 SET imm3, L
122	1100 1011 1100 0110 SET imm3, (HL)
123	1100 1011 1100 0111 SET imm3, A