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Add chip enable correctness for CellularRAM.
[firearm.git] / tests /
2010-03-12 Joshua WiseAdd support for CellularRAM on Nexys2. tree | commitdiff
2010-03-11 Joshua Wisetests/Makefile: Build without THUMB support. This... tree | commitdiff
2010-03-10 Joshua Wisetests/Makefile: Build the testbench by default with... tree | commitdiff
2009-03-18 Joshua WiseAdd testbench padded hex. tree | commitdiff
2009-03-18 Joshua Wisetestbench: Add a putc(getc()) loop. tree | commitdiff
2009-01-25 Joshua Wisetests/Makefile: Add a target to pad binaries for Xilinx... tree | commitdiff
2009-01-24 Joshua Wisetests/*.hex: Update hex files. tree | commitdiff
2009-01-24 Joshua Wisetests/miniblarg: Make the ROM easier to read. tree | commitdiff
2009-01-23 Joshua Wisetests/u-boot.hex: Add initial hex file. tree | commitdiff
2009-01-22 Joshua Wisetests/testbench: Commit new .hex file built with -O3... tree | commitdiff
2009-01-18 Joshua Wisetests/testbench: Add miniblarg. Put ldm_bonehead in... tree | commitdiff
2009-01-18 Joshua Wisetests/Makefile: Add CFLAGS for LOL2FAST2FURIOUS. tree | commitdiff
2009-01-17 Joshua Wisetests/testbench: Update output formatting for testbench. tree | commitdiff
2009-01-15 Joshua Wisetests/testbench: Allow compilation on x86. tree | commitdiff
2009-01-14 Joshua Wisetests/costas: respin .hex tree | commitdiff
2009-01-14 Joshua Wisetests: Add the new testbench. tree | commitdiff
2009-01-14 Joshua Wiseanulib: move the stack ALL the way up tree | commitdiff
2009-01-13 Joshua Wiseanulib: Move the stack up. tree | commitdiff
2009-01-11 Joshua WiseCostas: Remove while(1) and allow proper returns. tree | commitdiff
2009-01-10 Joshua WiseEnable part 2 of the Costas test program. tree | commitdiff
2009-01-10 Joshua WiseAdd tests directory. tree | commitdiff
FireARM pipelined ARM-like CPU implementation in Verilog
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