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Memory: Fix FSM for LDR/STR. Fix pre/post increment to be, uh, pre/post increment...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sun, 11 Jan 2009 04:41:07 +0000 (23:41 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sun, 11 Jan 2009 04:41:07 +0000 (23:41 -0500)
commitfeb2b5beb6bd3dbeb10ce942e10fbdf5f3df261e
tree18819b32e5d55897a50f2f051ac8795c05d7f246tree | snapshot
parentac3ba6ad6814e7d0cfb296d8b699f5b3ed2632a5commit | diff
Memory: Fix FSM for LDR/STR.  Fix pre/post increment to be, uh, pre/post increment, not post/pre increment.
Memory.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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