DCache, ICache: Reset fill circuitry if a request is aborted while filling.

diff --git a/DCache.v b/DCache.v
index e1d5d82f76e5cdede350878e347eac86ffb71843..472e1279df886e938d4ae77f2b24ab44ba22c2e8 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -44,6 +44,8 @@ module DCache(
        wire [3:0] idx = addr[9:6];
        wire [21:0] tag = addr[31:10];
        
        wire [3:0] idx = addr[9:6];
        wire [21:0] tag = addr[31:10];
        

+       reg [31:0] prev_addr = 32'hFFFFFFFF;
+       

        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        
        always @(*) begin
        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        
        always @(*) begin


@@ -69,8 +71,11 @@ module DCache(
                end
        end
        
                end
        end
        

-       always @(posedge clk)
-               if (rd_req && !cache_hit) begin
+       always @(posedge clk) begin
+               prev_addr <= {addr[31:6], 6'b0};
+               if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))        /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+                       cache_fill_pos <= 0;
+               else if (rd_req && !cache_hit) begin

                        if (bus_ready) begin    /* Started the fill, and we have data. */
                                cache_data[idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                        if (bus_ready) begin    /* Started the fill, and we have data. */
                                cache_data[idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;


@@ -81,4 +86,5 @@ module DCache(
                        end
                end else if (wr_req && cache_hit)
                        cache_data[idx][addr[5:2]] = wr_data;
                        end
                end else if (wr_req && cache_hit)
                        cache_data[idx][addr[5:2]] = wr_data;

+       end

 endmodule
 endmodule

diff --git a/ICache.v b/ICache.v
index 2e28adfabd54e1a98c338332a6ef122439089000..8106259ef9a175a417ab22ccbe849f1b02d7deef 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -45,6 +45,8 @@ module ICache(
        wire [3:0] rd_idx = rd_addr[9:6];
        wire [21:0] rd_tag = rd_addr[31:10];
        
        wire [3:0] rd_idx = rd_addr[9:6];
        wire [21:0] rd_tag = rd_addr[31:10];
        

+       reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
+       

        wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
        
        always @(*) begin       /* XXX does this work nowadays? */
        wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
        
        always @(*) begin       /* XXX does this work nowadays? */


@@ -63,10 +65,13 @@ module ICache(
                        bus_rd = 0;
                end
        
                        bus_rd = 0;
                end
        

-       always @(posedge clk)
-               if (rd_req && !cache_hit) begin
+       always @(posedge clk) begin
+               prev_rd_addr <= {rd_addr[31:6], 6'b0};
+               if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))      /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+                       cache_fill_pos <= 0;
+               else if (rd_req && !cache_hit) begin

                        if (bus_ready) begin    /* Started the fill, and we have data. */
                        if (bus_ready) begin    /* Started the fill, and we have data. */

-                               $display("CACHE FILL: rq adr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
+                               $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);

                                cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */
                                cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */


@@ -75,4 +80,5 @@ module ICache(
                                end
                        end
                end
                                end
                        end
                end

+       end

 endmodule
 endmodule