Merge branch 'master' of nyus.joshuawise.com:/git/firearm

diff --combined Memory.v
index 9fb3db04bb4d6c642e3e5adfa7834ba76b5f4117,237817790431c5f164bc0f4aadf9713b2fd08f27..fb482b0c608ae0905c1de46d02ad673dfd49e0dd
--- 1/Memory.v
--- 2/Memory.v
+++ b/Memory.v
@@@ -22,6 -22,7 +22,7 @@@ module Memory
        input [31:0] insn,
        input [31:0] op0,
        input [31:0] op1,
+       input [31:0] op2,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
@@@ -78,8 -79,7 +79,8 @@@
                next_write_data = write_data;
                next_inc_next = 1'b0;
                outstall = 1'b0;
 -              
 +              next_regs = 16'b0;
 +
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: begin
@@@ -99,8 -99,7 +100,7 @@@
                                align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
                                
                                if(!insn[20]) begin
-                                       st_read = insn[15:12];
-                                       wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+                                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
                                end
                                else if(!inc_next) begin
                                        next_write_reg = 1'b1;
@@@ -120,66 -119,44 +120,66 @@@
                        busaddr = {op0[31:2], 2'b0};
                        rd_req = insn[20];
                        wr_req = ~insn[20];
 -                      casez(regs)
 -                      16'b???????????????1: begin
 -                              next_regs = regs;
 -                      end
 -                      16'b??????????????10: begin
 -                      end
 -                      16'b?????????????100: begin
 -                      end
 -                      16'b????????????1000: begin
 -                      end
 -                      16'b???????????10000: begin
 -                      end
 -                      16'b??????????100000: begin
 -                      end
 -                      16'b?????????1000000: begin
 -                      end
 -                      16'b????????10000000: begin
 +                      if(inc_next) begin
                        end
 -                      16'b???????100000000: begin
 -                      end
 -                      16'b??????1000000000: begin
 -                      end
 -                      16'b?????10000000000: begin
 -                      end
 -                      16'b????100000000000: begin
 -                      end
 -                      16'b???1000000000000: begin
 -                      end
 -                      16'b??10000000000000: begin
 -                      end
 -                      16'b?100000000000000: begin
 -                      end
 -                      16'b1000000000000000: begin
 -                      end
 -                      default: begin
 -                              next_inc_next = 1'b1;
 +                      else if(rw_wait)
 +                              next_regs = regs;
 +                      else begin
 +                              casez(regs)
 +                              16'b???????????????1: begin
 +                                      next_regs = regs & 16'b1111111111111110;
 +                              end
 +                              16'b??????????????10: begin
 +                                      next_regs = regs & 16'b1111111111111100;
 +                              end
 +                              16'b?????????????100: begin
 +                                      next_regs = regs & 16'b1111111111111000;
 +                              end
 +                              16'b????????????1000: begin
 +                                      next_regs = regs & 16'b1111111111110000;
 +                              end
 +                              16'b???????????10000: begin
 +                                      next_regs = regs & 16'b1111111111100000;
 +                              end
 +                              16'b??????????100000: begin
 +                                      next_regs = regs & 16'b1111111111000000;
 +                              end
 +                              16'b?????????1000000: begin
 +                                      next_regs = regs & 16'b1111111110000000;
 +                              end
 +                              16'b????????10000000: begin
 +                                      next_regs = regs & 16'b1111111100000000;
 +                              end
 +                              16'b???????100000000: begin
 +                                      next_regs = regs & 16'b1111111000000000;
 +                              end
 +                              16'b??????1000000000: begin
 +                                      next_regs = regs & 16'b1111110000000000;
 +                              end
 +                              16'b?????10000000000: begin
 +                                      next_regs = regs & 16'b1111100000000000;
 +                              end
 +                              16'b????100000000000: begin
 +                                      next_regs = regs & 16'b1111000000000000;
 +                              end
 +                              16'b???1000000000000: begin
 +                                      next_regs = regs & 16'b1110000000000000;
 +                              end
 +                              16'b??10000000000000: begin
 +                                      next_regs = regs & 16'b1100000000000000;
 +                              end
 +                              16'b?100000000000000: begin
 +                                      next_regs = regs & 16'b1000000000000000;
 +                              end
 +                              16'b1000000000000000: begin
 +                                      next_regs = 16'b0;
 +                              end
 +                              default: begin
 +                              end
 +                              endcase
 +                              next_inc_next = next_regs == 16'b0;
 +                              next_notdone = ~next_inc_next;
                        end
 -                      endcase
                end
                default: begin end
                endcase