Convert decode to... use decode constants.

diff --git a/Decode.v b/Decode.v
index d07b95a7d1d8f4e3b59fc48e4bfbaaf45f70011f..d817d13d636bf9283ed88b010c4d54153122d5f1 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -46,27 +46,27 @@ module Decode(
 
        always @(*)
                casez (insn)
 
        always @(*)
                casez (insn)

-               32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
-//             32'b????00001???????????????1001????,   /* Multiply long */
-               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
-               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
-               32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
-               32'b????00010?00????????00001001????,   /* Atomic swap */
-               32'b????000100101111111111110001????,   /* Branch and exchange */
-               32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
-               32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
-               32'b????011????????????????????1????,   /* Undefined. I hate ARM */
-               32'b????01??????????????????????????,   /* Single data transfer */
-               32'b????100?????????????????????????,   /* Block data transfer */
-               32'b????101?????????????????????????,   /* Branch */
-               32'b????110?????????????????????????,   /* Coprocessor data transfer */
-               32'b????1110???????????????????0????,   /* Coprocessor data op */
-               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
-               32'b????1111????????????????????????:   /* SWI */
+               `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+//             `DECODE_ALU_MUL_LONG,           /* Multiply long */
+               `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
+               `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
+               `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               `DECODE_ALU_SWP,                /* Atomic swap */
+               `DECODE_ALU_BX,                 /* Branch and exchange */
+               `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
+               `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
+               `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
+               `DECODE_LDRSTR,                 /* Single data transfer */
+               `DECODE_LDMSTM,                 /* Block data transfer */
+               `DECODE_BRANCH,                 /* Branch */
+               `DECODE_LDCSTC,                 /* Coprocessor data transfer */
+               `DECODE_CDP,                    /* Coprocessor data op */
+               `DECODE_MRCMCR,                 /* Coprocessor register transfer */
+               `DECODE_SWI:                    /* SWI */

                        rpc = inpc - 8;
                        rpc = inpc - 8;

-               32'b????00??????????????????????????:   /* ALU */
+               `DECODE_ALU:                    /* ALU */

                        rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
                        rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));

-               default:                                /* X everything else out */
+               default:                        /* X everything else out */

                        rpc = 32'hxxxxxxxx;
                endcase
 
                        rpc = 32'hxxxxxxxx;
                endcase
 


@@ -76,61 +76,61 @@ module Decode(
                read_2 = 4'hx;
                
                casez (insn)
                read_2 = 4'hx;
                
                casez (insn)

-               32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+               `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */

                begin
                        read_0 = insn[15:12]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                        read_2 = insn[11:8];  /* Rs */
                end
                begin
                        read_0 = insn[15:12]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                        read_2 = insn[11:8];  /* Rs */
                end

-//             32'b????00001???????????????1001????,   /* Multiply long */
+//             `DECODE_ALU_MUL_LONG:   /* Multiply long */

 //                     read_0 = insn[11:8]; /* Rn */
 //                     read_1 = insn[3:0];   /* Rm */
 //                     read_2 = 4'b0;       /* anyus */
 //                     read_0 = insn[11:8]; /* Rn */
 //                     read_1 = insn[3:0];   /* Rm */
 //                     read_2 = 4'b0;       /* anyus */

-               32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
+               `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */

                begin end
                begin end

-               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
-               32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
+               `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */

                        read_0 = insn[3:0];     /* Rm */
                        read_0 = insn[3:0];     /* Rm */

-               32'b????00??????????????????????????:   /* ALU */
+               `DECODE_ALU_SWP:        /* Atomic swap */

                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */

-                       read_2 = insn[11:8];  /* Rs for shift */

                end
                end

-               32'b????00010?00????????00001001????:   /* Atomic swap */
-               begin
-                       read_0 = insn[19:16]; /* Rn */
-                       read_1 = insn[3:0];   /* Rm */
-               end
-               32'b????000100101111111111110001????:   /* Branch and exchange */
+               `DECODE_ALU_BX:         /* Branch and exchange */

                        read_0 = insn[3:0];   /* Rn */
                        read_0 = insn[3:0];   /* Rn */

-               32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
+               `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */

                begin
                        read_0 = insn[19:16];
                        read_1 = insn[3:0];
                end
                begin
                        read_0 = insn[19:16];
                        read_1 = insn[3:0];
                end

-               32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
+               `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */

                begin
                        read_0 = insn[19:16];
                end
                begin
                        read_0 = insn[19:16];
                end

-               32'b????011????????????????????1????:   /* Undefined. I hate ARM */
+               `DECODE_ALU:            /* ALU */
+               begin
+                       read_0 = insn[19:16]; /* Rn */
+                       read_1 = insn[3:0];   /* Rm */
+                       read_2 = insn[11:8];  /* Rs for shift */
+               end
+               `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */

                begin end
                begin end

-               32'b????01??????????????????????????:   /* Single data transfer */
+               `DECODE_LDRSTR:         /* Single data transfer */

                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                end
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                end

-               32'b????100?????????????????????????:   /* Block data transfer */
+               `DECODE_LDMSTM:         /* Block data transfer */

                        read_0 = insn[19:16];
                        read_0 = insn[19:16];

-               32'b????101?????????????????????????:   /* Branch */
+               `DECODE_BRANCH:         /* Branch */

                begin end
                begin end

-               32'b????110?????????????????????????:   /* Coprocessor data transfer */
+               `DECODE_LDCSTC:         /* Coprocessor data transfer */

                        read_0 = insn[19:16];
                        read_0 = insn[19:16];

-               32'b????1110???????????????????0????:   /* Coprocessor data op */
+               `DECODE_CDP:            /* Coprocessor data op */

                begin end
                begin end

-               32'b????1110???????????????????1????:   /* Coprocessor register transfer */
+               `DECODE_MRCMCR:         /* Coprocessor register transfer */

                        read_0 = insn[15:12];
                        read_0 = insn[15:12];

-               32'b????1111????????????????????????:   /* SWI */
+               `DECODE_SWI:            /* SWI */

                begin end
                default:
                        $display("Undecoded instruction");
                begin end
                default:
                        $display("Undecoded instruction");


@@ -143,55 +143,55 @@ module Decode(
                op2_out = 32'hxxxxxxxx;
                carry_out = 1'bx;
                casez (insn)
                op2_out = 32'hxxxxxxxx;
                carry_out = 1'bx;
                casez (insn)

-               32'b????000000??????????????1001????: begin /* Multiply */
+               `DECODE_ALU_MULT: begin         /* Multiply */

                        op0_out = regs0;
                        op1_out = regs1;
                        op2_out = regs2;
                end
                        op0_out = regs0;
                        op1_out = regs1;
                        op2_out = regs2;
                end

-//             32'b????00001???????????????1001????: begin /* Multiply long */
+//             `DECODE_ALU_MULT_LONG: begin    /* Multiply long */

 //                     op1_res = regs1;
 //             end
 //                     op1_res = regs1;
 //             end

-               32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
+               `DECODE_ALU_MRS: begin          /* MRS (Transfer PSR to register) */

                end
                end

-               32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
+               `DECODE_ALU_MSR: begin          /* MSR (Transfer register to PSR) */

                        op0_out = regs0;
                end
                        op0_out = regs0;
                end

-                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                `DECODE_ALU_MSR_FLAGS: begin   /* MSR (Transfer register or immediate to PSR, flag bits only) */

                        if(insn[25]) begin     /* the constant case */
                                op0_out = rotate_res;
                        end else begin
                                op0_out = regs0;
                        end
                 end
                        if(insn[25]) begin     /* the constant case */
                                op0_out = rotate_res;
                        end else begin
                                op0_out = regs0;
                        end
                 end

-               32'b????00??????????????????????????: begin /* ALU */
-                       op0_out = regs0;
-                       if(insn[25]) begin     /* the constant case */
-                               carry_out = incpsr[`CPSR_C];
-                               op1_out = rotate_res;
-                       end else begin
-                               carry_out = shift_cflag_out;
-                               op1_out = shift_res;
-                       end
-               end
-               32'b????00010?00????????00001001????: begin /* Atomic swap */
+               `DECODE_ALU_SWP: begin          /* Atomic swap */

                        op0_out = regs0;
                        op1_out = regs1;
                end
                        op0_out = regs0;
                        op1_out = regs1;
                end

-               32'b????000100101111111111110001????: begin /* Branch and exchange */
+               `DECODE_ALU_BX: begin           /* Branch and exchange */

                        op0_out = regs0;
                end
                        op0_out = regs0;
                end

-               32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
+               `DECODE_ALU_HDATA_REG: begin    /* Halfword transfer - register offset */

                        op0_out = regs0;
                        op1_out = regs1;
                end
                        op0_out = regs0;
                        op1_out = regs1;
                end

-               32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
+               `DECODE_ALU_HDATA_IMM: begin    /* Halfword transfer - immediate offset */

                        op0_out = regs0;
                        op1_out = {24'b0, insn[11:8], insn[3:0]};
                end
                        op0_out = regs0;
                        op1_out = {24'b0, insn[11:8], insn[3:0]};
                end

-               32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
+               `DECODE_ALU: begin              /* ALU */
+                       op0_out = regs0;
+                       if(insn[25]) begin     /* the constant case */
+                               carry_out = incpsr[`CPSR_C];
+                               op1_out = rotate_res;
+                       end else begin
+                               carry_out = shift_cflag_out;
+                               op1_out = shift_res;
+                       end
+               end
+               `DECODE_LDRSTR_UNDEFINED: begin /* Undefined. I hate ARM */

                        /* eat shit */
                end
                        /* eat shit */
                end

-               32'b????01??????????????????????????: begin /* Single data transfer */
+               `DECODE_LDRSTR: begin           /* Single data transfer */

                        op0_out = regs0;
                        if(insn[25]) begin
                                op1_out = {20'b0, insn[11:0]};
                        op0_out = regs0;
                        if(insn[25]) begin
                                op1_out = {20'b0, insn[11:0]};


@@ -201,23 +201,23 @@ module Decode(
                                carry_out = shift_cflag_out;
                        end
                end
                                carry_out = shift_cflag_out;
                        end
                end

-               32'b????100?????????????????????????: begin /* Block data transfer */
+               `DECODE_LDMSTM: begin           /* Block data transfer */

                        op0_out = regs0;
                        op1_out = {16'b0, insn[15:0]};
                end
                        op0_out = regs0;
                        op1_out = {16'b0, insn[15:0]};
                end

-               32'b????101?????????????????????????: begin /* Branch */
+               `DECODE_BRANCH: begin           /* Branch */

                        op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
                end
                        op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
                end

-               32'b????110?????????????????????????: begin /* Coprocessor data transfer */
+               `DECODE_LDCSTC: begin           /* Coprocessor data transfer */

                        op0_out = regs0;
                        op1_out = {24'b0, insn[7:0]};
                end
                        op0_out = regs0;
                        op1_out = {24'b0, insn[7:0]};
                end

-               32'b????1110???????????????????0????: begin /* Coprocessor data op */
+               `DECODE_CDP: begin              /* Coprocessor data op */

                end
                end

-               32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
+               `DECODE_MRCMCR: begin           /* Coprocessor register transfer */

                        op0_out = regs0;
                end
                        op0_out = regs0;
                end

-               32'b????1111????????????????????????: begin /* SWI */
+               `DECODE_SWI: begin              /* SWI */

                end
                default: begin end
                endcase
                end
                default: begin end
                endcase