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DCache, ICache: Move curdata out to its own wire for synthesis. Fix up a blocking...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 08:56:01 +0000 (03:56 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 24 Jan 2009 08:56:01 +0000 (03:56 -0500)
commitac760abbb074404374f0b376981d5b1c695ac9b3
tree170b490faa9c2502b3c3c4b654feb1444f6a68f5tree | snapshot
parent8b09558c6aa1ac41a28e9a16d5764df5af5704eecommit | diff
DCache, ICache: Move curdata out to its own wire for synthesis.  Fix up a blocking assign that should be a nonblocking assign.
DCache.v diff | blob | blame | history
ICache.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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