* 0x00004000. rdata and ready must be driven to zero if the
* address is not within the range of this module.
*/
- wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
+ wire decode = bus_addr[31:14] == 18'b0;
wire [13:0] ramaddr = {bus_addr[13:2], 2'b0}; /* mask off lower two bits
* for word alignment */
always @(posedge clk)
begin
if (bus_wr && decode)
- data[ramaddr[13:2]] <= bus_wdata;
+ data[ramaddr[13:2]] = bus_wdata;
/* This is not allowed to be conditional -- stupid Xilinx
* blockram. */