Fetch: Rewrite for the 317235784th time, this time based off a block diagram on paper...

[firearm.git] / BlockRAM.v

diff --git a/BlockRAM.v b/BlockRAM.v
index 30f7515c698dc33d7de61d5ae55a6e1b0f9ec937..091c749aef6f8f482bfbfe3025c881608d1696ff 100644 (file)
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -12,7 +12,7 @@ module BlockRAM(
         * 0x00004000.  rdata and ready must be driven to zero if the
         * address is not within the range of this module.
         */
-       wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
+       wire decode = bus_addr[31:14] == 18'b0;
        wire [13:0] ramaddr = {bus_addr[13:2], 2'b0};   /* mask off lower two bits
                                                         * for word alignment */
 
@@ -35,7 +35,7 @@ module BlockRAM(
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */
-               temprdata <= data[ramaddr[13:2]];
+               temprdata <= (bus_wr && decode) ? bus_wdata : data[ramaddr[13:2]];
                lastread <= ramaddr;
        end
 endmodule