`define BUS_ICACHE 1
`define BUS_DCACHE 0
-module System(input clk);
+module System(input clk
+`ifdef verilator
+`else
+ , output wire [8:0] sys_odata,
+ input [8:0] sys_idata,
+ output wire sys_tookdata
+`endif
+ );
+
wire [7:0] bus_req;
wire [7:0] bus_ack;
wire [31:0] bus_addr;
.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
- BlockRAM blockram(
+`ifdef verilator
+ BigBlockRAM
+`else
+ BlockRAM
+`endif
+ blockram(
.clk(clk),
.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
Terminal terminal(
.clk(clk),
.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
- .cp_read(cp_read_terminal), .cp_write(cp_write));
+ .cp_read(cp_read_terminal), .cp_write(cp_write)
+`ifdef verilator
+`else
+ , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
+`endif
+ );
Writeback writeback(
.clk(clk),