Fetch: Fix async reset to actually not do it wrong.

[firearm.git] / system.v

diff --git a/system.v b/system.v
index 17412039d77b1b7827a0e8a4adb27ea797ac17d1..07adfd88ac963c3c908c9602b2161f3dfe96533e 100644 (file)
--- a/system.v
+++ b/system.v
@@ -127,7 +127,12 @@ module System(input clk);
                .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
                .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
 
-       BlockRAM blockram(
+`ifdef verilator
+       BigBlockRAM
+`else
+       BlockRAM
+`endif
+       blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
                .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),