`define BUS_ICACHE 1
`define BUS_DCACHE 0
-module System(input clk);
+module System(input clk, input rst
+`ifdef verilator
+`else
+ , output wire [8:0] sys_odata,
+ input [8:0] sys_idata,
+ output wire sys_tookdata
+`endif
+ );
+
wire [7:0] bus_req;
wire [7:0] bus_ack;
wire [31:0] bus_addr;
wire [31:0] pc_out_issue;
wire [31:0] pc_out_execute;
wire [31:0] pc_out_memory;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
+ wire [31:0] ic__rd_data_1a; // From icache of ICache.v
+ wire ic__rd_req_0a; // From fetch of Fetch.v
+ wire ic__rd_wait_0a; // From icache of ICache.v
+ // End of automatics
wire execute_out_backflush;
wire writeback_out_backflush;
BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
- ICache icache(
+ /* XXX reset? */
+ /* ICache AUTO_TEMPLATE (
.clk(clk),
- /* XXX reset? */
- .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
- .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
- .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
- .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
- .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
+ .bus_req(bus_req_icache),
+ .bus_ack(bus_ack_icache),
+ .bus_addr(bus_addr_icache),
+ .bus_rdata(bus_rdata),
+ .bus_wdata(bus_wdata_icache),
+ .bus_rd(bus_rd_icache),
+ .bus_wr(bus_wr_icache),
+ .bus_ready(bus_ready),
+ ); */
+ ICache icache(/*AUTOINST*/
+ // Outputs
+ .ic__rd_wait_0a (ic__rd_wait_0a),
+ .ic__rd_data_1a (ic__rd_data_1a[31:0]),
+ .bus_req (bus_req_icache), // Templated
+ .bus_addr (bus_addr_icache), // Templated
+ .bus_wdata (bus_wdata_icache), // Templated
+ .bus_rd (bus_rd_icache), // Templated
+ .bus_wr (bus_wr_icache), // Templated
+ // Inputs
+ .clk (clk), // Templated
+ .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
+ .ic__rd_req_0a (ic__rd_req_0a),
+ .bus_ack (bus_ack_icache), // Templated
+ .bus_rdata (bus_rdata), // Templated
+ .bus_ready (bus_ready)); // Templated
DCache dcache(
.clk(clk),
.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
- BlockRAM blockram(
+`ifdef verilator
+ BigBlockRAM
+`else
+ BlockRAM
+`endif
+ blockram(
.clk(clk),
.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
.bus_ready(bus_ready_blockram));
- Fetch fetch(
+ /* Fetch AUTO_TEMPLATE (
.clk(clk),
- .Nrst(1'b1 /* XXX */),
- .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
- .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
- .bubble(bubble_out_fetch), .insn(insn_out_fetch),
- .pc(pc_out_fetch));
+ .Nrst(~rst),
+ .stall_0a(stall_cause_issue),
+ .jmp_0a(jmp),
+ .jmppc_0a(jmppc),
+ .bubble_1a(bubble_out_fetch),
+ .insn_1a(insn_out_fetch),
+ .pc_1a(pc_out_fetch),
+ );
+ */
+ Fetch fetch(
+ /*AUTOINST*/
+ // Outputs
+ .ic__rd_addr_0a (ic__rd_addr_0a[31:0]),
+ .ic__rd_req_0a (ic__rd_req_0a),
+ .bubble_1a (bubble_out_fetch), // Templated
+ .insn_1a (insn_out_fetch), // Templated
+ .pc_1a (pc_out_fetch), // Templated
+ // Inputs
+ .clk (clk), // Templated
+ .Nrst (~rst), // Templated
+ .ic__rd_wait_0a (ic__rd_wait_0a),
+ .ic__rd_data_1a (ic__rd_data_1a[31:0]),
+ .stall_0a (stall_cause_issue), // Templated
+ .jmp_0a (jmp), // Templated
+ .jmppc_0a (jmppc)); // Templated
Issue issue(
.clk(clk),
- .Nrst(1'b1 /* XXX */),
+ .Nrst(~rst),
.stall(stall_cause_execute), .flush(execute_out_backflush | writeback_out_backflush),
.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
.inpc(pc_out_fetch), .cpsr(writeback_out_cpsr),
.outpc(pc_out_issue), .outinsn(insn_out_issue));
RegFile regfile(
- .clk(clk),
+ .clk(clk), .Nrst(~rst),
.read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), .read_3(regfile_read_3),
.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2), .rdata_3(regfile_rdata_3),
.spsr(regfile_spsr),
.rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
Execute execute(
- .clk(clk), .Nrst(1'b0),
+ .clk(clk), .Nrst(~rst),
.stall(stall_cause_memory), .flush(writeback_out_backflush),
.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
.cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
assign cp_insn = insn_out_execute;
Memory memory(
- .clk(clk), .Nrst(1'b0),
+ .clk(clk), .Nrst(~rst),
/* stall? */ .flush(writeback_out_backflush),
.busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
.rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
Terminal terminal(
.clk(clk),
.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
- .cp_read(cp_read_terminal), .cp_write(cp_write));
+ .cp_read(cp_read_terminal), .cp_write(cp_write)
+`ifdef verilator
+`else
+ , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
+`endif
+ );
Writeback writeback(
.clk(clk),
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