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Memory: Add CDP and MRC/MCR.
[firearm.git] / ram.hex
diff --git a/ram.hex b/ram.hex
index 9f19cbb..1a068cc 100644 (file)
--- a/ram.hex
+++ b/ram.hex
@@ -21,9 +21,9 @@ E180F081
 E180F081
 E180F081
 EA000000
-EBFFFFFF
+EAFFFFFE
 E1A00000
-EAFFFFFD
+EBFFFFFC
 E0000000
 E0000000
 E0000000
FireARM pipelined ARM-like CPU implementation in Verilog
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