+ cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
+ if(cur_reg == 4'hF && insn[22]) begin
+ next_outcpsr = spsr;
+ end
+
+ if(rw_wait) begin
+ next_regs = regs;
+ cur_reg = prev_reg;
+ raddr = prev_raddr;
+ end
+ else begin
+ offset = prev_offset + 6'h4;
+ offset_sel = insn[24] ? offset : prev_offset;
+ raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+ if(insn[20]) begin
+ next_write_reg = 1'b1;
+ next_write_num = cur_reg;
+ next_write_data = rd_data;
+ end
+ end
+
+ st_read = cur_reg;
+ wr_data = st_data;
+ busaddr = {raddr[31:2], 2'b0};
+
+ outstall = 1'b1;
+
+ if(next_regs == 16'b0) begin
+ next_lsm_state = 3'b100;
+ end
+ end
+ 3'b100: begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
+ next_lsm_state = 3'b001;
+ end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: if(!inbubble) begin
+ $display("WARNING: Unimplemented LDCSTC");
+ end
+ `DECODE_CDP: if(!inbubble) begin
+ cp_req = 1;
+ if (cp_busy) begin
+ outstall = 1;
+ next_outbubble = 1;
+ end
+ if (!cp_ack) begin
+ /* XXX undefined instruction trap */
+ $display("WARNING: Possible CDP undefined instruction");
+ end
+ end
+ `DECODE_MRCMCR: if(!inbubble) begin
+ cp_req = 1;
+ cp_rnw = insn[20] /* L */;
+ if (insn[20] == 0 /* store to coprocessor */)
+ cp_write = op0;
+ else begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[15:12];
+ next_write_data = cp_read;
+ end
+ if (cp_busy) begin
+ outstall = 1;
+ next_outbubble = 1;
+ end
+ if (!cp_ack) begin
+ $display("WARNING: Possible MRCMCR undefined instruction");