+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* Bus data control logic. */
+ always @(*)
+ begin
+ dc__wr_data_3a = 32'hxxxxxxxx;
+
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a)
+ if (swp_state == `SWP_WRITING)
+ dc__wr_data_3a = insn_3a[22] ? {4{op1_3a[7:0]}} : op1_3a;
+ `DECODE_ALU_MULT: begin end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a)
+ case(insn_3a[6:5])
+ 2'b01: /* unsigned half */
+ dc__wr_data_3a = {2{op2_3a[15:0]}}; /* XXX need to store halfword */
+ 2'b10: /* signed byte */
+ dc__wr_data_3a = {4{op2_3a[7:0]}};
+ 2'b11: /* signed half */
+ dc__wr_data_3a = {2{op2_3a[15:0]}};
+ default: begin end
+ endcase
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!bubble_3a) begin
+ dc__wr_data_3a = insn_3a[22] ? {24'h0, {op2_3a[7:0]}} : op2_3a;
+ if (lsr_state == `LSR_STRB_WR)
+ case (dc__addr_3a[1:0])
+ 2'b00: dc__wr_data_3a = {rd_data_latch[31:8], op2_3a[7:0]};
+ 2'b01: dc__wr_data_3a = {rd_data_latch[31:16], op2_3a[7:0], rd_data_latch[7:0]};
+ 2'b10: dc__wr_data_3a = {rd_data_latch[31:24], op2_3a[7:0], rd_data_latch[15:0]};
+ 2'b11: dc__wr_data_3a = {op2_3a[7:0], rd_data_latch[23:0]};
+ endcase
+ end
+ `DECODE_LDMSTM: if (!bubble_3a)
+ if (lsm_state == `LSM_MEMIO)
+ dc__wr_data_3a = (cur_reg == 4'hF) ? (pc_3a + 12) : rf__rdata_3_3a;
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* LDM/STM register control logic. */
+ always @(posedge clk)
+ if (!dc__rw_wait_3a || lsm_state != `LSM_MEMIO)
+ begin
+ prev_reg <= cur_reg;
+ regs <= next_regs;
+ end
+
+ always @(*)
+ begin
+ rf__read_3_3a = 4'hx;
+ cur_reg = prev_reg;
+ next_regs = regs;
+
+ casez(insn_3a)
+ `DECODE_LDMSTM: if(!bubble_3a) begin
+ case(lsm_state)
+ `LSM_SETUP:
+ next_regs = insn_3a[23] /* U */ ? op1_3a[15:0] : {op1_3a[0], op1_3a[1], op1_3a[2], op1_3a[3], op1_3a[4], op1_3a[5], op1_3a[6], op1_3a[7],
+ op1_3a[8], op1_3a[9], op1_3a[10], op1_3a[11], op1_3a[12], op1_3a[13], op1_3a[14], op1_3a[15]};
+ `LSM_MEMIO: begin
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = {regs[15:1], 1'b0};
+ end
+ 16'b??????????????10: begin
+ cur_reg = 4'h1;
+ next_regs = {regs[15:2], 2'b0};
+ end
+ 16'b?????????????100: begin
+ cur_reg = 4'h2;
+ next_regs = {regs[15:3], 3'b0};
+ end
+ 16'b????????????1000: begin
+ cur_reg = 4'h3;
+ next_regs = {regs[15:4], 4'b0};
+ end
+ 16'b???????????10000: begin
+ cur_reg = 4'h4;
+ next_regs = {regs[15:5], 5'b0};
+ end
+ 16'b??????????100000: begin
+ cur_reg = 4'h5;
+ next_regs = {regs[15:6], 6'b0};
+ end
+ 16'b?????????1000000: begin
+ cur_reg = 4'h6;
+ next_regs = {regs[15:7], 7'b0};
+ end
+ 16'b????????10000000: begin
+ cur_reg = 4'h7;
+ next_regs = {regs[15:8], 8'b0};
+ end
+ 16'b???????100000000: begin
+ cur_reg = 4'h8;
+ next_regs = {regs[15:9], 9'b0};
+ end
+ 16'b??????1000000000: begin
+ cur_reg = 4'h9;
+ next_regs = {regs[15:10], 10'b0};
+ end
+ 16'b?????10000000000: begin
+ cur_reg = 4'hA;
+ next_regs = {regs[15:11], 11'b0};
+ end
+ 16'b????100000000000: begin
+ cur_reg = 4'hB;
+ next_regs = {regs[15:12], 12'b0};
+ end
+ 16'b???1000000000000: begin
+ cur_reg = 4'hC;
+ next_regs = {regs[15:13], 13'b0};
+ end
+ 16'b??10000000000000: begin
+ cur_reg = 4'hD;
+ next_regs = {regs[15:14], 14'b0};
+ end
+ 16'b?100000000000000: begin
+ cur_reg = 4'hE;
+ next_regs = {regs[15], 15'b0};
+ end
+ 16'b1000000000000000: begin
+ cur_reg = 4'hF;
+ next_regs = 16'b0;
+ end
+ default: begin
+ cur_reg = 4'hx;
+ next_regs = 16'b0;
+ end
+ endcase
+ cur_reg = insn_3a[23] ? cur_reg : 4'hF - cur_reg;
+
+ rf__read_3_3a = cur_reg;
+ end
+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ endcase
+ end
+
+ always @(*)
+ begin
+ do_rd_data_latch = 0;
+
+ next_outbubble = bubble_3a;
+
+ lsrh_rddata = 32'hxxxxxxxx;
+ lsrh_rddata_s1 = 16'hxxxx;
+ lsrh_rddata_s2 = 8'hxx;
+ next_swp_oldval = swp_oldval;
+
+ align_s1 = 32'hxxxxxxxx;
+ align_s2 = 32'hxxxxxxxx;
+ align_rddata = 32'hxxxxxxxx;
+
+ /* XXX shit not given about endianness */
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a) begin
+ next_outbubble = dc__rw_wait_3a;
+ case(swp_state)
+ `SWP_READING:
+ if(!dc__rw_wait_3a)
+ next_swp_oldval = dc__rd_data_3a;
+ `SWP_WRITING: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ next_outbubble = bubble_3a; /* XXX workaround for Xilinx bug */
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
+ next_outbubble = dc__rw_wait_3a;
+
+ /* rotate to correct position */
+ case(insn_3a[6:5])
+ 2'b01: begin /* unsigned half */
+ lsrh_rddata = {16'b0, raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0]};
+ end
+ 2'b10: begin /* signed byte */
+ lsrh_rddata_s1 = raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0];
+ lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
+ lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
+ end
+ 2'b11: begin /* signed half */
+ lsrh_rddata = raddr[1] ? {{16{dc__rd_data_3a[31]}}, dc__rd_data_3a[31:16]} : {{16{dc__rd_data_3a[15]}}, dc__rd_data_3a[15:0]};