with more reg

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index 7d7f95b67859b1a9f0f9fb8b315b1dc48ea3b1a8..689e8fc3d6e879d97d9ff9229d21f8ed00e5fa23 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -10,22 +10,24 @@ module Decode(
        output reg [31:0] op2,
        output reg carry,
 
-       output [3:0] read_0,
-       output [3:0] read_1,
-       output [3:0] read_2,
+       output reg [3:0] read_0,
+       output reg [3:0] read_1,
+       output reg [3:0] read_2,
        input [31:0] rdata_0,
        input [31:0] rdata_1,
        input [31:0] rdata_2
        );
 
-       wire [31:0] regs0, regs1, regs2, rpc;
-       wire [31:0] op0_out, op1_out, op2_out;
-       wire carry_out;
+       wire [31:0] regs0, regs1, regs2;
+       reg [31:0] rpc;
+       reg [31:0] op0_out, op1_out, op2_out;
+       reg carry_out;
 
        /* shifter stuff */
        wire [31:0] shift_oper;
        wire [31:0] shift_res;
        wire shift_cflag_out;
+       wire [31:0] rotate_res;
 
        assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
        assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
@@ -38,6 +40,10 @@ module Decode(
                                   .res(shift_res),
                                   .cflag_out(shift_cflag_out));
 
+       SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
+                             .amt(insn[11:8]),
+                             .res(rotate_res));
+
        always @(*)
                casez (insn)
                32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
@@ -152,7 +158,7 @@ module Decode(
                end
                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
                        if(insn[25]) begin     /* the constant case */
-                               op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
+                               op0_out = rotate_res;
                        end else begin
                                op0_out = regs0;
                        end
@@ -161,7 +167,7 @@ module Decode(
                        op0_out = regs0;
                        if(insn[25]) begin     /* the constant case */
                                carry_out = incpsr[`CPSR_C];
-                               op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
+                               op1_out = rotate_res;
                        end else begin
                                carry_out = shift_cflag_out;
                                op1_out = shift_res;
@@ -231,12 +237,12 @@ module IREALLYHATEARMSHIFT(
        input [31:0] operand,
        input [31:0] reg_amt,
        input cflag_in,
-       output [31:0] res,
-       output cflag_out
+       output reg [31:0] res,
+       output reg cflag_out
 );
        wire [5:0] shift_amt;
-       wire rshift_cout, is_arith, is_rot;
-       wire [31:0] rshift_res;
+       reg rshift_cout, is_arith, is_rot;
+       reg [31:0] rshift_res;
 
        assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
                                   : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
@@ -252,6 +258,7 @@ module IREALLYHATEARMSHIFT(
        always @(*)
                case (insn[6:5])
                `SHIFT_LSL: begin
+                       /* meaningless */
                        is_rot = 1'b0;
                        is_arith = 1'b0;
                end
@@ -285,7 +292,7 @@ module IREALLYHATEARMSHIFT(
                        if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
                                res = {cflag_in, operand[31:1]};
                                cflag_out = operand[0];
-                       else
+                       end else begin
                                res = rshift_res;
                                cflag_out = rshift_cout;
                        end
@@ -305,14 +312,28 @@ module SuckLessShifter(
 
        wire [32:0] stage1, stage2, stage3, stage4, stage5;
 
-       wire pushbits = is_arith & operand[31];
+       wire pushbits = is_arith & oper[31];
 
        /* do a barrel shift */
        assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
-       assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[16]} : stage1;
-       assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[8]} : stage2;
-       assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[4]} : stage3;
-       assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[2]} : stage4;
-       assign {res, carryout} = amt[0] ? {is_rot ? stage4[0] : pushbits, stage5[31:1], stage5[1]} : stage5;
+       assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
+       assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
+       assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
+       assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
+       assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
+
+endmodule
+
+module SuckLessRotator(
+       input [31:0] oper,
+       input [3:0] amt,
+       output [31:0] res
+);
+
+       wire [31:0] stage1, stage2, stage3;
+       assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
+       assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
+       assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
+       assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
 
 endmodule