Decode.v: shifter now less incorrect

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index 7d7f95b67859b1a9f0f9fb8b315b1dc48ea3b1a8..44a948ca209ec22fe4137689bcc24b3e5c527009 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -252,6 +252,7 @@ module IREALLYHATEARMSHIFT(
        always @(*)
                case (insn[6:5])
                `SHIFT_LSL: begin
+                       /* meaningless */
                        is_rot = 1'b0;
                        is_arith = 1'b0;
                end
@@ -285,7 +286,7 @@ module IREALLYHATEARMSHIFT(
                        if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
                                res = {cflag_in, operand[31:1]};
                                cflag_out = operand[0];
-                       else
+                       end else begin
                                res = rshift_res;
                                cflag_out = rshift_cout;
                        end
@@ -305,14 +306,14 @@ module SuckLessShifter(
 
        wire [32:0] stage1, stage2, stage3, stage4, stage5;
 
-       wire pushbits = is_arith & operand[31];
+       wire pushbits = is_arith & oper[31];
 
        /* do a barrel shift */
        assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
-       assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[16]} : stage1;
-       assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[8]} : stage2;
-       assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[4]} : stage3;
-       assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[2]} : stage4;
-       assign {res, carryout} = amt[0] ? {is_rot ? stage4[0] : pushbits, stage5[31:1], stage5[1]} : stage5;
+       assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
+       assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
+       assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
+       assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
+       assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;
 
 endmodule