reg cache_valid [15:0];
reg [21:0] cache_tags [15:0];
reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
-
- reg [4:0] i;
+
+ integer i;
initial
for (i = 0; i < 16; i = i + 1)
begin
if (cache_fill_pos == 15) begin /* Done? */
cache_tags[idx] <= tag;
cache_valid[idx] <= 1;
- end
+ end else
+ cache_valid[idx] <= 0;
end
end else if (wr_req && cache_hit)
cache_data[idx][addr[5:2]] = wr_data;