reg [1:0] lsr_state = 2'b01, next_lsr_state;
reg [31:0] align_s1, align_s2, align_rddata;
reg [1:0] lsr_state = 2'b01, next_lsr_state;
reg [31:0] align_s1, align_s2, align_rddata;
busaddr = raddr;
/* rotate to correct position */
align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
busaddr = raddr;
/* rotate to correct position */
align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;