assign bus_rd = bus_rd_icache;
assign bus_wr = bus_wr_icache;
assign bus_ready = bus_ready_blockram;
assign bus_rd = bus_rd_icache;
assign bus_wr = bus_wr_icache;
assign bus_ready = bus_ready_blockram;
wire execute_out_write_reg;
wire [3:0] execute_out_write_num;
wire [31:0] execute_out_write_data;
wire execute_out_write_reg;
wire [3:0] execute_out_write_num;
wire [31:0] execute_out_write_data;
wire [31:0] insn_out_issue;
wire [31:0] pc_out_fetch;
wire [31:0] pc_out_issue;
wire [31:0] insn_out_issue;
wire [31:0] pc_out_fetch;
wire [31:0] pc_out_issue;
.Nrst(1'b1 /* XXX */),
.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
.Nrst(1'b1 /* XXX */),
.rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
.rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
- .stall(stall_cause_issue), .jmp(1'b0 /* XXX */), .jmppc(32'b0 /* XXX */),
+ .stall(stall_cause_issue), .jmp(jmp), .jmppc(jmppc),
.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
.inbubble(bubble_out_fetch), .insn(insn_out_fetch),
.inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
.outstall(stall_cause_issue), .outbubble(bubble_out_issue),
.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
.op2(decode_out_op2), .carry(decode_out_carry),
.outstall(stall_cause_execute), .outbubble(execute_out_bubble),
.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
.inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
.cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
.op2(decode_out_op2), .carry(decode_out_carry),
.outstall(stall_cause_execute), .outbubble(execute_out_bubble),
.write_reg(execute_out_write_reg), .write_num(execute_out_write_num),