+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ next_outbubble = rw_wait;
+ outstall = rw_wait;
+ addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+ raddr = insn[24] ? addr : op0; /* pre/post increment */
+ busaddr = raddr;
+ /* rotate to correct position */
+ align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+ align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+ /* select byte or word */
+ align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+ wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
+ data_size = insn[22] ? 3'b001 : 3'b100;
+ case(lsr_state)
+ 4'b0001: begin
+ rd_req = insn[20] /* L */ || insn[22] /* B */;
+ wr_req = !insn[20] /* L */ && !insn[22]/* B */;
+ next_write_reg = insn[20] /* L */;
+ next_write_num = insn[15:12];
+ if(insn[20] /* L */) begin
+ next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
+ end
+ if (insn[22] /* B */ && !insn[20] /* L */) begin
+ do_rd_data_latch = 1;
+ outstall = 1'b1;
+ if (!rw_wait)
+ next_lsr_state = 4'b0010; /* XXX: One-hot, my ass. */
+ end else if(insn[21] /* W */ | !insn[24] /* P */) begin
+ outstall = 1'b1;
+ if(!rw_wait)
+ next_lsr_state = 4'b0100;
+ end
+ $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
+ end
+ 4'b0010: begin
+ $display("LDRSTR: Handling STRB");
+ outstall = 1;
+ rd_req = 0;
+ wr_req = 1;
+ next_write_reg = 0;
+ case (busaddr[1:0])
+ 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
+ 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
+ 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
+ 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
+ endcase
+ if(insn[21] /* W */ | !insn[24] /* P */) begin
+ if(!rw_wait)
+ next_lsr_state = 4'b0100;
+ end else if (!rw_wait)
+ next_lsr_state = 4'b1000;
+ end
+ 4'b0100: begin
+ outstall = 1;
+ rd_req = 0;
+ wr_req= 0;
+ next_outbubble = 0;
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = addr;
+ next_lsr_state = 4'b1000;
+ end
+ 4'b1000: begin
+ rd_req = 0;
+ wr_req= 0;
+ outstall = 0;
+ next_lsr_state = 4'b0001;
+ end
+ default: begin end
+ endcase
+
+ if ((lsr_state == 4'b0001) && flush) begin /* Reject it. */
+ outstall = 1'b0;
+ next_lsr_state = 4'b0001;
+ end
+ end
+ /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
+ `DECODE_LDMSTM: if(!inbubble) begin
+ outstall = rw_wait;
+ next_outbubble = rw_wait;
+ data_size = 3'b100;
+ case(lsm_state)
+ 4'b0001: begin